1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260
#[doc = "Reader of register AHB2LPENR"] pub type R = crate::R<u32, super::AHB2LPENR>; #[doc = "Writer for register AHB2LPENR"] pub type W = crate::W<u32, super::AHB2LPENR>; #[doc = "Register AHB2LPENR `reset()`'s with value 0xf1"] impl crate::ResetValue for super::AHB2LPENR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0xf1 } } #[doc = "USB OTG FS clock enable during Sleep mode\n\nValue on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum OTGFSLPEN_A { #[doc = "0: Selected module is disabled during Sleep mode"] DISABLEDINSLEEP = 0, #[doc = "1: Selected module is enabled during Sleep mode"] ENABLEDINSLEEP = 1, } impl From<OTGFSLPEN_A> for bool { #[inline(always)] fn from(variant: OTGFSLPEN_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `OTGFSLPEN`"] pub type OTGFSLPEN_R = crate::R<bool, OTGFSLPEN_A>; impl OTGFSLPEN_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> OTGFSLPEN_A { match self.bits { false => OTGFSLPEN_A::DISABLEDINSLEEP, true => OTGFSLPEN_A::ENABLEDINSLEEP, } } #[doc = "Checks if the value of the field is `DISABLEDINSLEEP`"] #[inline(always)] pub fn is_disabled_in_sleep(&self) -> bool { *self == OTGFSLPEN_A::DISABLEDINSLEEP } #[doc = "Checks if the value of the field is `ENABLEDINSLEEP`"] #[inline(always)] pub fn is_enabled_in_sleep(&self) -> bool { *self == OTGFSLPEN_A::ENABLEDINSLEEP } } #[doc = "Write proxy for field `OTGFSLPEN`"] pub struct OTGFSLPEN_W<'a> { w: &'a mut W, } impl<'a> OTGFSLPEN_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: OTGFSLPEN_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Selected module is disabled during Sleep mode"] #[inline(always)] pub fn disabled_in_sleep(self) -> &'a mut W { self.variant(OTGFSLPEN_A::DISABLEDINSLEEP) } #[doc = "Selected module is enabled during Sleep mode"] #[inline(always)] pub fn enabled_in_sleep(self) -> &'a mut W { self.variant(OTGFSLPEN_A::ENABLEDINSLEEP) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); self.w } } #[doc = "RNGLPEN"] pub type RNGLPEN_A = OTGFSLPEN_A; #[doc = "Reader of field `RNGLPEN`"] pub type RNGLPEN_R = crate::R<bool, OTGFSLPEN_A>; #[doc = "Write proxy for field `RNGLPEN`"] pub struct RNGLPEN_W<'a> { w: &'a mut W, } impl<'a> RNGLPEN_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: RNGLPEN_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Selected module is disabled during Sleep mode"] #[inline(always)] pub fn disabled_in_sleep(self) -> &'a mut W { self.variant(OTGFSLPEN_A::DISABLEDINSLEEP) } #[doc = "Selected module is enabled during Sleep mode"] #[inline(always)] pub fn enabled_in_sleep(self) -> &'a mut W { self.variant(OTGFSLPEN_A::ENABLEDINSLEEP) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); self.w } } #[doc = "Flexible memory controller module clock enable during Sleep mode"] pub type FSMCLPEN_A = OTGFSLPEN_A; #[doc = "Reader of field `FSMCLPEN`"] pub type FSMCLPEN_R = crate::R<bool, OTGFSLPEN_A>; #[doc = "Write proxy for field `FSMCLPEN`"] pub struct FSMCLPEN_W<'a> { w: &'a mut W, } impl<'a> FSMCLPEN_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: FSMCLPEN_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Selected module is disabled during Sleep mode"] #[inline(always)] pub fn disabled_in_sleep(self) -> &'a mut W { self.variant(OTGFSLPEN_A::DISABLEDINSLEEP) } #[doc = "Selected module is enabled during Sleep mode"] #[inline(always)] pub fn enabled_in_sleep(self) -> &'a mut W { self.variant(OTGFSLPEN_A::ENABLEDINSLEEP) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } #[doc = "QUADSPI memory controller module clock enable during Sleep mode"] pub type QSPILPEN_A = OTGFSLPEN_A; #[doc = "Reader of field `QSPILPEN`"] pub type QSPILPEN_R = crate::R<bool, OTGFSLPEN_A>; #[doc = "Write proxy for field `QSPILPEN`"] pub struct QSPILPEN_W<'a> { w: &'a mut W, } impl<'a> QSPILPEN_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: QSPILPEN_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Selected module is disabled during Sleep mode"] #[inline(always)] pub fn disabled_in_sleep(self) -> &'a mut W { self.variant(OTGFSLPEN_A::DISABLEDINSLEEP) } #[doc = "Selected module is enabled during Sleep mode"] #[inline(always)] pub fn enabled_in_sleep(self) -> &'a mut W { self.variant(OTGFSLPEN_A::ENABLEDINSLEEP) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } impl R { #[doc = "Bit 7 - USB OTG FS clock enable during Sleep mode"] #[inline(always)] pub fn otgfslpen(&self) -> OTGFSLPEN_R { OTGFSLPEN_R::new(((self.bits >> 7) & 0x01) != 0) } #[doc = "Bit 6 - RNGLPEN"] #[inline(always)] pub fn rnglpen(&self) -> RNGLPEN_R { RNGLPEN_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode"] #[inline(always)] pub fn fsmclpen(&self) -> FSMCLPEN_R { FSMCLPEN_R::new((self.bits & 0x01) != 0) } #[doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode"] #[inline(always)] pub fn qspilpen(&self) -> QSPILPEN_R { QSPILPEN_R::new(((self.bits >> 1) & 0x01) != 0) } } impl W { #[doc = "Bit 7 - USB OTG FS clock enable during Sleep mode"] #[inline(always)] pub fn otgfslpen(&mut self) -> OTGFSLPEN_W { OTGFSLPEN_W { w: self } } #[doc = "Bit 6 - RNGLPEN"] #[inline(always)] pub fn rnglpen(&mut self) -> RNGLPEN_W { RNGLPEN_W { w: self } } #[doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode"] #[inline(always)] pub fn fsmclpen(&mut self) -> FSMCLPEN_W { FSMCLPEN_W { w: self } } #[doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode"] #[inline(always)] pub fn qspilpen(&mut self) -> QSPILPEN_W { QSPILPEN_W { w: self } } }