Module stm32f334::adc1_2
[−]
[src]
Analog-to-Digital Converter
Modules
| awd2cr |
Analog Watchdog 2 Configuration Register |
| awd3cr |
Analog Watchdog 3 Configuration Register |
| calfact |
Calibration Factors |
| ccr |
ADC common control register |
| cdr |
ADC common regular data register for dual and triple modes |
| cfgr |
configuration register |
| cr |
control register |
| csr |
ADC Common status register |
| difsel |
Differential Mode Selection Register 2 |
| dr |
regular Data Register |
| ier |
interrupt enable register |
| isr |
interrupt and status register |
| jdr1 |
injected data register 1 |
| jdr2 |
injected data register 2 |
| jdr3 |
injected data register 3 |
| jdr4 |
injected data register 4 |
| jsqr |
injected sequence register |
| ofr1 |
offset register 1 |
| ofr2 |
offset register 2 |
| ofr3 |
offset register 3 |
| ofr4 |
offset register 4 |
| smpr1 |
sample time register 1 |
| smpr2 |
sample time register 2 |
| sqr1 |
regular sequence register 1 |
| sqr2 |
regular sequence register 2 |
| sqr3 |
regular sequence register 3 |
| sqr4 |
regular sequence register 4 |
| tr1 |
watchdog threshold register 1 |
| tr2 |
watchdog threshold register |
| tr3 |
watchdog threshold register 3 |
Structs
| AWD2CR |
Analog Watchdog 2 Configuration Register |
| AWD3CR |
Analog Watchdog 3 Configuration Register |
| CALFACT |
Calibration Factors |
| CCR |
ADC common control register |
| CDR |
ADC common regular data register for dual and triple modes |
| CFGR |
configuration register |
| CR |
control register |
| CSR |
ADC Common status register |
| DIFSEL |
Differential Mode Selection Register 2 |
| DR |
regular Data Register |
| IER |
interrupt enable register |
| ISR |
interrupt and status register |
| JDR1 |
injected data register 1 |
| JDR2 |
injected data register 2 |
| JDR3 |
injected data register 3 |
| JDR4 |
injected data register 4 |
| JSQR |
injected sequence register |
| OFR1 |
offset register 1 |
| OFR2 |
offset register 2 |
| OFR3 |
offset register 3 |
| OFR4 |
offset register 4 |
| RegisterBlock |
Register block |
| SMPR1 |
sample time register 1 |
| SMPR2 |
sample time register 2 |
| SQR1 |
regular sequence register 1 |
| SQR2 |
regular sequence register 2 |
| SQR3 |
regular sequence register 3 |
| SQR4 |
regular sequence register 4 |
| TR1 |
watchdog threshold register 1 |
| TR2 |
watchdog threshold register |
| TR3 |
watchdog threshold register 3 |