Struct stm32f30x::dma1::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub isr: Isr,
    pub ifcr: Ifcr,
    pub ccr1: Ccr1,
    pub cndtr1: Cndtr1,
    pub cpar1: Cpar1,
    pub cmar1: Cmar1,
    pub ccr2: Ccr2,
    pub cndtr2: Cndtr2,
    pub cpar2: Cpar2,
    pub cmar2: Cmar2,
    pub ccr3: Ccr3,
    pub cndtr3: Cndtr3,
    pub cpar3: Cpar3,
    pub cmar3: Cmar3,
    pub ccr4: Ccr4,
    pub cndtr4: Cndtr4,
    pub cpar4: Cpar4,
    pub cmar4: Cmar4,
    pub ccr5: Ccr5,
    pub cndtr5: Cndtr5,
    pub cpar5: Cpar5,
    pub cmar5: Cmar5,
    pub ccr6: Ccr6,
    pub cndtr6: Cndtr6,
    pub cpar6: Cpar6,
    pub cmar6: Cmar6,
    pub ccr7: Ccr7,
    pub cndtr7: Cndtr7,
    pub cpar7: Cpar7,
    pub cmar7: Cmar7,
    // some fields omitted
}

Register block

Fields

isr: Isr

0x00 - DMA interrupt status register (DMA_ISR)

ifcr: Ifcr

0x04 - DMA interrupt flag clear register (DMA_IFCR)

ccr1: Ccr1

0x08 - DMA channel configuration register (DMA_CCR)

cndtr1: Cndtr1

0x0c - DMA channel 1 number of data register

cpar1: Cpar1

0x10 - DMA channel 1 peripheral address register

cmar1: Cmar1

0x14 - DMA channel 1 memory address register

ccr2: Ccr2

0x1c - DMA channel configuration register (DMA_CCR)

cndtr2: Cndtr2

0x20 - DMA channel 2 number of data register

cpar2: Cpar2

0x24 - DMA channel 2 peripheral address register

cmar2: Cmar2

0x28 - DMA channel 2 memory address register

ccr3: Ccr3

0x30 - DMA channel configuration register (DMA_CCR)

cndtr3: Cndtr3

0x34 - DMA channel 3 number of data register

cpar3: Cpar3

0x38 - DMA channel 3 peripheral address register

cmar3: Cmar3

0x3c - DMA channel 3 memory address register

ccr4: Ccr4

0x44 - DMA channel configuration register (DMA_CCR)

cndtr4: Cndtr4

0x48 - DMA channel 4 number of data register

cpar4: Cpar4

0x4c - DMA channel 4 peripheral address register

cmar4: Cmar4

0x50 - DMA channel 4 memory address register

ccr5: Ccr5

0x58 - DMA channel configuration register (DMA_CCR)

cndtr5: Cndtr5

0x5c - DMA channel 5 number of data register

cpar5: Cpar5

0x60 - DMA channel 5 peripheral address register

cmar5: Cmar5

0x64 - DMA channel 5 memory address register

ccr6: Ccr6

0x6c - DMA channel configuration register (DMA_CCR)

cndtr6: Cndtr6

0x70 - DMA channel 6 number of data register

cpar6: Cpar6

0x74 - DMA channel 6 peripheral address register

cmar6: Cmar6

0x78 - DMA channel 6 memory address register

ccr7: Ccr7

0x80 - DMA channel configuration register (DMA_CCR)

cndtr7: Cndtr7

0x84 - DMA channel 7 number of data register

cpar7: Cpar7

0x88 - DMA channel 7 peripheral address register

cmar7: Cmar7

0x8c - DMA channel 7 memory address register