1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
#[doc = "Reader of register SMCR"] pub type R = crate::R<u32, super::SMCR>; #[doc = "Writer for register SMCR"] pub type W = crate::W<u32, super::SMCR>; #[doc = "Register SMCR `reset()`'s with value 0"] impl crate::ResetValue for super::SMCR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `MSM`"] pub type MSM_R = crate::R<bool, bool>; #[doc = "Write proxy for field `MSM`"] pub struct MSM_W<'a> { w: &'a mut W, } impl<'a> MSM_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); self.w } } #[doc = "Reader of field `TS`"] pub type TS_R = crate::R<u8, u8>; #[doc = "Write proxy for field `TS`"] pub struct TS_W<'a> { w: &'a mut W, } impl<'a> TS_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4); self.w } } #[doc = "Reader of field `SMS`"] pub type SMS_R = crate::R<u8, u8>; #[doc = "Write proxy for field `SMS`"] pub struct SMS_W<'a> { w: &'a mut W, } impl<'a> SMS_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); self.w } } impl R { #[doc = "Bit 7 - Master/Slave mode"] #[inline(always)] pub fn msm(&self) -> MSM_R { MSM_R::new(((self.bits >> 7) & 0x01) != 0) } #[doc = "Bits 4:6 - Trigger selection"] #[inline(always)] pub fn ts(&self) -> TS_R { TS_R::new(((self.bits >> 4) & 0x07) as u8) } #[doc = "Bits 0:2 - Slave mode selection"] #[inline(always)] pub fn sms(&self) -> SMS_R { SMS_R::new((self.bits & 0x07) as u8) } } impl W { #[doc = "Bit 7 - Master/Slave mode"] #[inline(always)] pub fn msm(&mut self) -> MSM_W { MSM_W { w: self } } #[doc = "Bits 4:6 - Trigger selection"] #[inline(always)] pub fn ts(&mut self) -> TS_W { TS_W { w: self } } #[doc = "Bits 0:2 - Slave mode selection"] #[inline(always)] pub fn sms(&mut self) -> SMS_W { SMS_W { w: self } } }