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#[doc = r"Value read from the register"] pub struct R { bits: u32, } #[doc = r"Value to write to the register"] pub struct W { bits: u32, } impl super::CFR { #[doc = r"Modifies the contents of the register"] #[inline(always)] pub fn modify<F>(&self, f: F) where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set(f(&R { bits }, &mut W { bits }).bits); } #[doc = r"Reads the contents of the register"] #[inline(always)] pub fn read(&self) -> R { R { bits: self.register.get(), } } #[doc = r"Writes to the register"] #[inline(always)] pub fn write<F>(&self, f: F) where F: FnOnce(&mut W) -> &mut W, { self.register.set( f(&mut W { bits: Self::reset_value(), }) .bits, ); } #[doc = r"Reset value of the register"] #[inline(always)] pub const fn reset_value() -> u32 { 0x7f } #[doc = r"Writes the reset value to the register"] #[inline(always)] pub fn reset(&self) { self.register.set(Self::reset_value()) } } #[doc = "Possible values of the field `EWI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EWIR { #[doc = "interrupt occurs whenever the counter reaches the value 0x40"] ENABLE, #[doc = r"Reserved"] _Reserved(bool), } impl EWIR { #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { match *self { EWIR::ENABLE => true, EWIR::_Reserved(bits) => bits, } } #[allow(missing_docs)] #[doc(hidden)] #[inline(always)] pub fn _from(value: bool) -> EWIR { match value { true => EWIR::ENABLE, i => EWIR::_Reserved(i), } } #[doc = "Checks if the value of the field is `ENABLE`"] #[inline(always)] pub fn is_enable(&self) -> bool { *self == EWIR::ENABLE } } #[doc = "Values that can be written to the field `EWI`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum EWIW { #[doc = "interrupt occurs whenever the counter reaches the value 0x40"] ENABLE, } impl EWIW { #[allow(missing_docs)] #[doc(hidden)] #[inline(always)] pub fn _bits(&self) -> bool { match *self { EWIW::ENABLE => true, } } } #[doc = r"Proxy"] pub struct _EWIW<'a> { w: &'a mut W, } impl<'a> _EWIW<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: EWIW) -> &'a mut W { { self.bit(variant._bits()) } } #[doc = "interrupt occurs whenever the counter reaches the value 0x40"] #[inline(always)] pub fn enable(self) -> &'a mut W { self.variant(EWIW::ENABLE) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits &= !(0x01 << 9); self.w.bits |= ((value as u32) & 0x01) << 9; self.w } } #[doc = r"Value of the field"] pub struct WR { bits: u8, } impl WR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { self.bits } } #[doc = r"Proxy"] pub struct _WW<'a> { w: &'a mut W, } impl<'a> _WW<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x7f << 0); self.w.bits |= ((value as u32) & 0x7f) << 0; self.w } } #[doc = "Possible values of the field `WDGTB`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WDGTBR { #[doc = "Counter clock (PCLK1 div 4096) div 1"] DIV1, #[doc = "Counter clock (PCLK1 div 4096) div 2"] DIV2, #[doc = "Counter clock (PCLK1 div 4096) div 4"] DIV4, #[doc = "Counter clock (PCLK1 div 4096) div 8"] DIV8, } impl WDGTBR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { match *self { WDGTBR::DIV1 => 0, WDGTBR::DIV2 => 0x01, WDGTBR::DIV4 => 0x02, WDGTBR::DIV8 => 0x03, } } #[allow(missing_docs)] #[doc(hidden)] #[inline(always)] pub fn _from(value: u8) -> WDGTBR { match value { 0 => WDGTBR::DIV1, 1 => WDGTBR::DIV2, 2 => WDGTBR::DIV4, 3 => WDGTBR::DIV8, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `DIV1`"] #[inline(always)] pub fn is_div1(&self) -> bool { *self == WDGTBR::DIV1 } #[doc = "Checks if the value of the field is `DIV2`"] #[inline(always)] pub fn is_div2(&self) -> bool { *self == WDGTBR::DIV2 } #[doc = "Checks if the value of the field is `DIV4`"] #[inline(always)] pub fn is_div4(&self) -> bool { *self == WDGTBR::DIV4 } #[doc = "Checks if the value of the field is `DIV8`"] #[inline(always)] pub fn is_div8(&self) -> bool { *self == WDGTBR::DIV8 } } #[doc = "Values that can be written to the field `WDGTB`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WDGTBW { #[doc = "Counter clock (PCLK1 div 4096) div 1"] DIV1, #[doc = "Counter clock (PCLK1 div 4096) div 2"] DIV2, #[doc = "Counter clock (PCLK1 div 4096) div 4"] DIV4, #[doc = "Counter clock (PCLK1 div 4096) div 8"] DIV8, } impl WDGTBW { #[allow(missing_docs)] #[doc(hidden)] #[inline(always)] pub fn _bits(&self) -> u8 { match *self { WDGTBW::DIV1 => 0, WDGTBW::DIV2 => 1, WDGTBW::DIV4 => 2, WDGTBW::DIV8 => 3, } } } #[doc = r"Proxy"] pub struct _WDGTBW<'a> { w: &'a mut W, } impl<'a> _WDGTBW<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: WDGTBW) -> &'a mut W { { self.bits(variant._bits()) } } #[doc = "Counter clock (PCLK1 div 4096) div 1"] #[inline(always)] pub fn div1(self) -> &'a mut W { self.variant(WDGTBW::DIV1) } #[doc = "Counter clock (PCLK1 div 4096) div 2"] #[inline(always)] pub fn div2(self) -> &'a mut W { self.variant(WDGTBW::DIV2) } #[doc = "Counter clock (PCLK1 div 4096) div 4"] #[inline(always)] pub fn div4(self) -> &'a mut W { self.variant(WDGTBW::DIV4) } #[doc = "Counter clock (PCLK1 div 4096) div 8"] #[inline(always)] pub fn div8(self) -> &'a mut W { self.variant(WDGTBW::DIV8) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x03 << 7); self.w.bits |= ((value as u32) & 0x03) << 7; self.w } } impl R { #[doc = r"Value of the register as raw bits"] #[inline(always)] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bit 9 - Early wakeup interrupt"] #[inline(always)] pub fn ewi(&self) -> EWIR { EWIR::_from(((self.bits >> 9) & 0x01) != 0) } #[doc = "Bits 0:6 - 7-bit window value"] #[inline(always)] pub fn w(&self) -> WR { let bits = ((self.bits >> 0) & 0x7f) as u8; WR { bits } } #[doc = "Bits 7:8 - Timer base"] #[inline(always)] pub fn wdgtb(&self) -> WDGTBR { WDGTBR::_from(((self.bits >> 7) & 0x03) as u8) } } impl W { #[doc = r"Writes raw bits to the register"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; self } #[doc = "Bit 9 - Early wakeup interrupt"] #[inline(always)] pub fn ewi(&mut self) -> _EWIW { _EWIW { w: self } } #[doc = "Bits 0:6 - 7-bit window value"] #[inline(always)] pub fn w(&mut self) -> _WW { _WW { w: self } } #[doc = "Bits 7:8 - Timer base"] #[inline(always)] pub fn wdgtb(&mut self) -> _WDGTBW { _WDGTBW { w: self } } }