#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFGR3 {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `USART1SW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USART1SWR {
#[doc = "PCLK selected as USART clock source"]
PCLK,
#[doc = "SYSCLK selected as USART clock source"]
SYSCLK,
#[doc = "LSE selected as USART clock source"]
LSE,
#[doc = "HSI selected as USART clock source"]
HSI,
}
impl USART1SWR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
USART1SWR::PCLK => 0,
USART1SWR::SYSCLK => 0x01,
USART1SWR::LSE => 0x02,
USART1SWR::HSI => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> USART1SWR {
match value {
0 => USART1SWR::PCLK,
1 => USART1SWR::SYSCLK,
2 => USART1SWR::LSE,
3 => USART1SWR::HSI,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PCLK`"]
#[inline(always)]
pub fn is_pclk(&self) -> bool {
*self == USART1SWR::PCLK
}
#[doc = "Checks if the value of the field is `SYSCLK`"]
#[inline(always)]
pub fn is_sysclk(&self) -> bool {
*self == USART1SWR::SYSCLK
}
#[doc = "Checks if the value of the field is `LSE`"]
#[inline(always)]
pub fn is_lse(&self) -> bool {
*self == USART1SWR::LSE
}
#[doc = "Checks if the value of the field is `HSI`"]
#[inline(always)]
pub fn is_hsi(&self) -> bool {
*self == USART1SWR::HSI
}
}
#[doc = "Values that can be written to the field `USART1SW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USART1SWW {
#[doc = "PCLK selected as USART clock source"]
PCLK,
#[doc = "SYSCLK selected as USART clock source"]
SYSCLK,
#[doc = "LSE selected as USART clock source"]
LSE,
#[doc = "HSI selected as USART clock source"]
HSI,
}
impl USART1SWW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
USART1SWW::PCLK => 0,
USART1SWW::SYSCLK => 1,
USART1SWW::LSE => 2,
USART1SWW::HSI => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _USART1SWW<'a> {
w: &'a mut W,
}
impl<'a> _USART1SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: USART1SWW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "PCLK selected as USART clock source"]
#[inline(always)]
pub fn pclk(self) -> &'a mut W {
self.variant(USART1SWW::PCLK)
}
#[doc = "SYSCLK selected as USART clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(USART1SWW::SYSCLK)
}
#[doc = "LSE selected as USART clock source"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(USART1SWW::LSE)
}
#[doc = "HSI selected as USART clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(USART1SWW::HSI)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 0);
self.w.bits |= ((value as u32) & 0x03) << 0;
self.w
}
}
#[doc = "Possible values of the field `I2C1SW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C1SWR {
#[doc = "HSI clock selected as I2C clock source"]
HSI,
#[doc = "SYSCLK clock selected as I2C clock source"]
SYSCLK,
}
impl I2C1SWR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
I2C1SWR::HSI => false,
I2C1SWR::SYSCLK => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> I2C1SWR {
match value {
false => I2C1SWR::HSI,
true => I2C1SWR::SYSCLK,
}
}
#[doc = "Checks if the value of the field is `HSI`"]
#[inline(always)]
pub fn is_hsi(&self) -> bool {
*self == I2C1SWR::HSI
}
#[doc = "Checks if the value of the field is `SYSCLK`"]
#[inline(always)]
pub fn is_sysclk(&self) -> bool {
*self == I2C1SWR::SYSCLK
}
}
#[doc = "Values that can be written to the field `I2C1SW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C1SWW {
#[doc = "HSI clock selected as I2C clock source"]
HSI,
#[doc = "SYSCLK clock selected as I2C clock source"]
SYSCLK,
}
impl I2C1SWW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
I2C1SWW::HSI => false,
I2C1SWW::SYSCLK => true,
}
}
}
#[doc = r"Proxy"]
pub struct _I2C1SWW<'a> {
w: &'a mut W,
}
impl<'a> _I2C1SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2C1SWW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "HSI clock selected as I2C clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(I2C1SWW::HSI)
}
#[doc = "SYSCLK clock selected as I2C clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(I2C1SWW::SYSCLK)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 4);
self.w.bits |= ((value as u32) & 0x01) << 4;
self.w
}
}
#[doc = "Possible values of the field `I2C2SW`"]
pub type I2C2SWR = I2C1SWR;
#[doc = "Values that can be written to the field `I2C2SW`"]
pub type I2C2SWW = I2C1SWW;
#[doc = r"Proxy"]
pub struct _I2C2SWW<'a> {
w: &'a mut W,
}
impl<'a> _I2C2SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2C2SWW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "HSI clock selected as I2C clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(I2C1SWW::HSI)
}
#[doc = "SYSCLK clock selected as I2C clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(I2C1SWW::SYSCLK)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 5);
self.w.bits |= ((value as u32) & 0x01) << 5;
self.w
}
}
#[doc = "Possible values of the field `I2C3SW`"]
pub type I2C3SWR = I2C1SWR;
#[doc = "Values that can be written to the field `I2C3SW`"]
pub type I2C3SWW = I2C1SWW;
#[doc = r"Proxy"]
pub struct _I2C3SWW<'a> {
w: &'a mut W,
}
impl<'a> _I2C3SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2C3SWW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "HSI clock selected as I2C clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(I2C1SWW::HSI)
}
#[doc = "SYSCLK clock selected as I2C clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(I2C1SWW::SYSCLK)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 6);
self.w.bits |= ((value as u32) & 0x01) << 6;
self.w
}
}
#[doc = "Possible values of the field `USART2SW`"]
pub type USART2SWR = USART1SWR;
#[doc = "Values that can be written to the field `USART2SW`"]
pub type USART2SWW = USART1SWW;
#[doc = r"Proxy"]
pub struct _USART2SWW<'a> {
w: &'a mut W,
}
impl<'a> _USART2SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: USART2SWW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "PCLK selected as USART clock source"]
#[inline(always)]
pub fn pclk(self) -> &'a mut W {
self.variant(USART1SWW::PCLK)
}
#[doc = "SYSCLK selected as USART clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(USART1SWW::SYSCLK)
}
#[doc = "LSE selected as USART clock source"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(USART1SWW::LSE)
}
#[doc = "HSI selected as USART clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(USART1SWW::HSI)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 16);
self.w.bits |= ((value as u32) & 0x03) << 16;
self.w
}
}
#[doc = "Possible values of the field `USART3SW`"]
pub type USART3SWR = USART1SWR;
#[doc = "Values that can be written to the field `USART3SW`"]
pub type USART3SWW = USART1SWW;
#[doc = r"Proxy"]
pub struct _USART3SWW<'a> {
w: &'a mut W,
}
impl<'a> _USART3SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: USART3SWW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "PCLK selected as USART clock source"]
#[inline(always)]
pub fn pclk(self) -> &'a mut W {
self.variant(USART1SWW::PCLK)
}
#[doc = "SYSCLK selected as USART clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(USART1SWW::SYSCLK)
}
#[doc = "LSE selected as USART clock source"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(USART1SWW::LSE)
}
#[doc = "HSI selected as USART clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(USART1SWW::HSI)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 18);
self.w.bits |= ((value as u32) & 0x03) << 18;
self.w
}
}
#[doc = "Possible values of the field `TIM1SW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TIM1SWR {
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
PCLK2,
#[doc = "PLL vco output (running up to 144 MHz)"]
PLL,
}
impl TIM1SWR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
TIM1SWR::PCLK2 => false,
TIM1SWR::PLL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> TIM1SWR {
match value {
false => TIM1SWR::PCLK2,
true => TIM1SWR::PLL,
}
}
#[doc = "Checks if the value of the field is `PCLK2`"]
#[inline(always)]
pub fn is_pclk2(&self) -> bool {
*self == TIM1SWR::PCLK2
}
#[doc = "Checks if the value of the field is `PLL`"]
#[inline(always)]
pub fn is_pll(&self) -> bool {
*self == TIM1SWR::PLL
}
}
#[doc = "Values that can be written to the field `TIM1SW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TIM1SWW {
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
PCLK2,
#[doc = "PLL vco output (running up to 144 MHz)"]
PLL,
}
impl TIM1SWW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
TIM1SWW::PCLK2 => false,
TIM1SWW::PLL => true,
}
}
}
#[doc = r"Proxy"]
pub struct _TIM1SWW<'a> {
w: &'a mut W,
}
impl<'a> _TIM1SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM1SWW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SWW::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SWW::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 8);
self.w.bits |= ((value as u32) & 0x01) << 8;
self.w
}
}
#[doc = "Possible values of the field `TIM8SW`"]
pub type TIM8SWR = TIM1SWR;
#[doc = "Values that can be written to the field `TIM8SW`"]
pub type TIM8SWW = TIM1SWW;
#[doc = r"Proxy"]
pub struct _TIM8SWW<'a> {
w: &'a mut W,
}
impl<'a> _TIM8SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM8SWW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SWW::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SWW::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 9);
self.w.bits |= ((value as u32) & 0x01) << 9;
self.w
}
}
#[doc = "Possible values of the field `UART4SW`"]
pub type UART4SWR = USART1SWR;
#[doc = "Values that can be written to the field `UART4SW`"]
pub type UART4SWW = USART1SWW;
#[doc = r"Proxy"]
pub struct _UART4SWW<'a> {
w: &'a mut W,
}
impl<'a> _UART4SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: UART4SWW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "PCLK selected as USART clock source"]
#[inline(always)]
pub fn pclk(self) -> &'a mut W {
self.variant(USART1SWW::PCLK)
}
#[doc = "SYSCLK selected as USART clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(USART1SWW::SYSCLK)
}
#[doc = "LSE selected as USART clock source"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(USART1SWW::LSE)
}
#[doc = "HSI selected as USART clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(USART1SWW::HSI)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 20);
self.w.bits |= ((value as u32) & 0x03) << 20;
self.w
}
}
#[doc = "Possible values of the field `UART5SW`"]
pub type UART5SWR = USART1SWR;
#[doc = "Values that can be written to the field `UART5SW`"]
pub type UART5SWW = USART1SWW;
#[doc = r"Proxy"]
pub struct _UART5SWW<'a> {
w: &'a mut W,
}
impl<'a> _UART5SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: UART5SWW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "PCLK selected as USART clock source"]
#[inline(always)]
pub fn pclk(self) -> &'a mut W {
self.variant(USART1SWW::PCLK)
}
#[doc = "SYSCLK selected as USART clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(USART1SWW::SYSCLK)
}
#[doc = "LSE selected as USART clock source"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(USART1SWW::LSE)
}
#[doc = "HSI selected as USART clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(USART1SWW::HSI)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 22);
self.w.bits |= ((value as u32) & 0x03) << 22;
self.w
}
}
#[doc = "Possible values of the field `TIM20SW`"]
pub type TIM20SWR = TIM1SWR;
#[doc = "Values that can be written to the field `TIM20SW`"]
pub type TIM20SWW = TIM1SWW;
#[doc = r"Proxy"]
pub struct _TIM20SWW<'a> {
w: &'a mut W,
}
impl<'a> _TIM20SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM20SWW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SWW::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SWW::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 15);
self.w.bits |= ((value as u32) & 0x01) << 15;
self.w
}
}
#[doc = "Possible values of the field `TIM15SW`"]
pub type TIM15SWR = TIM1SWR;
#[doc = "Values that can be written to the field `TIM15SW`"]
pub type TIM15SWW = TIM1SWW;
#[doc = r"Proxy"]
pub struct _TIM15SWW<'a> {
w: &'a mut W,
}
impl<'a> _TIM15SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM15SWW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SWW::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SWW::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 10);
self.w.bits |= ((value as u32) & 0x01) << 10;
self.w
}
}
#[doc = "Possible values of the field `TIM16SW`"]
pub type TIM16SWR = TIM1SWR;
#[doc = "Values that can be written to the field `TIM16SW`"]
pub type TIM16SWW = TIM1SWW;
#[doc = r"Proxy"]
pub struct _TIM16SWW<'a> {
w: &'a mut W,
}
impl<'a> _TIM16SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM16SWW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SWW::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SWW::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 11);
self.w.bits |= ((value as u32) & 0x01) << 11;
self.w
}
}
#[doc = "Possible values of the field `TIM17SW`"]
pub type TIM17SWR = TIM1SWR;
#[doc = "Values that can be written to the field `TIM17SW`"]
pub type TIM17SWW = TIM1SWW;
#[doc = r"Proxy"]
pub struct _TIM17SWW<'a> {
w: &'a mut W,
}
impl<'a> _TIM17SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM17SWW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SWW::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SWW::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 13);
self.w.bits |= ((value as u32) & 0x01) << 13;
self.w
}
}
#[doc = "Possible values of the field `TIM2SW`"]
pub type TIM2SWR = TIM1SWR;
#[doc = "Values that can be written to the field `TIM2SW`"]
pub type TIM2SWW = TIM1SWW;
#[doc = r"Proxy"]
pub struct _TIM2SWW<'a> {
w: &'a mut W,
}
impl<'a> _TIM2SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM2SWW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SWW::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SWW::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 24);
self.w.bits |= ((value as u32) & 0x01) << 24;
self.w
}
}
#[doc = "Possible values of the field `TIM34SW`"]
pub type TIM34SWR = TIM1SWR;
#[doc = "Values that can be written to the field `TIM34SW`"]
pub type TIM34SWW = TIM1SWW;
#[doc = r"Proxy"]
pub struct _TIM34SWW<'a> {
w: &'a mut W,
}
impl<'a> _TIM34SWW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM34SWW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SWW::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SWW::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 25);
self.w.bits |= ((value as u32) & 0x01) << 25;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - USART1 clock source selection"]
#[inline(always)]
pub fn usart1sw(&self) -> USART1SWR {
USART1SWR::_from(((self.bits >> 0) & 0x03) as u8)
}
#[doc = "Bit 4 - I2C1 clock source selection"]
#[inline(always)]
pub fn i2c1sw(&self) -> I2C1SWR {
I2C1SWR::_from(((self.bits >> 4) & 0x01) != 0)
}
#[doc = "Bit 5 - I2C2 clock source selection"]
#[inline(always)]
pub fn i2c2sw(&self) -> I2C2SWR {
I2C2SWR::_from(((self.bits >> 5) & 0x01) != 0)
}
#[doc = "Bit 6 - I2C3 clock source selection"]
#[inline(always)]
pub fn i2c3sw(&self) -> I2C3SWR {
I2C3SWR::_from(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bits 16:17 - USART2 clock source selection"]
#[inline(always)]
pub fn usart2sw(&self) -> USART2SWR {
USART2SWR::_from(((self.bits >> 16) & 0x03) as u8)
}
#[doc = "Bits 18:19 - USART3 clock source selection"]
#[inline(always)]
pub fn usart3sw(&self) -> USART3SWR {
USART3SWR::_from(((self.bits >> 18) & 0x03) as u8)
}
#[doc = "Bit 8 - Timer1 clock source selection"]
#[inline(always)]
pub fn tim1sw(&self) -> TIM1SWR {
TIM1SWR::_from(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 9 - Timer8 clock source selection"]
#[inline(always)]
pub fn tim8sw(&self) -> TIM8SWR {
TIM8SWR::_from(((self.bits >> 9) & 0x01) != 0)
}
#[doc = "Bits 20:21 - UART4 clock source selection"]
#[inline(always)]
pub fn uart4sw(&self) -> UART4SWR {
UART4SWR::_from(((self.bits >> 20) & 0x03) as u8)
}
#[doc = "Bits 22:23 - UART5 clock source selection"]
#[inline(always)]
pub fn uart5sw(&self) -> UART5SWR {
UART5SWR::_from(((self.bits >> 22) & 0x03) as u8)
}
#[doc = "Bit 15 - Timer20 clock source selection"]
#[inline(always)]
pub fn tim20sw(&self) -> TIM20SWR {
TIM20SWR::_from(((self.bits >> 15) & 0x01) != 0)
}
#[doc = "Bit 10 - Timer15 clock source selection"]
#[inline(always)]
pub fn tim15sw(&self) -> TIM15SWR {
TIM15SWR::_from(((self.bits >> 10) & 0x01) != 0)
}
#[doc = "Bit 11 - Timer16 clock source selection"]
#[inline(always)]
pub fn tim16sw(&self) -> TIM16SWR {
TIM16SWR::_from(((self.bits >> 11) & 0x01) != 0)
}
#[doc = "Bit 13 - Timer17 clock source selection"]
#[inline(always)]
pub fn tim17sw(&self) -> TIM17SWR {
TIM17SWR::_from(((self.bits >> 13) & 0x01) != 0)
}
#[doc = "Bit 24 - Timer2 clock source selection"]
#[inline(always)]
pub fn tim2sw(&self) -> TIM2SWR {
TIM2SWR::_from(((self.bits >> 24) & 0x01) != 0)
}
#[doc = "Bit 25 - Timer34 clock source selection"]
#[inline(always)]
pub fn tim34sw(&self) -> TIM34SWR {
TIM34SWR::_from(((self.bits >> 25) & 0x01) != 0)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - USART1 clock source selection"]
#[inline(always)]
pub fn usart1sw(&mut self) -> _USART1SWW {
_USART1SWW { w: self }
}
#[doc = "Bit 4 - I2C1 clock source selection"]
#[inline(always)]
pub fn i2c1sw(&mut self) -> _I2C1SWW {
_I2C1SWW { w: self }
}
#[doc = "Bit 5 - I2C2 clock source selection"]
#[inline(always)]
pub fn i2c2sw(&mut self) -> _I2C2SWW {
_I2C2SWW { w: self }
}
#[doc = "Bit 6 - I2C3 clock source selection"]
#[inline(always)]
pub fn i2c3sw(&mut self) -> _I2C3SWW {
_I2C3SWW { w: self }
}
#[doc = "Bits 16:17 - USART2 clock source selection"]
#[inline(always)]
pub fn usart2sw(&mut self) -> _USART2SWW {
_USART2SWW { w: self }
}
#[doc = "Bits 18:19 - USART3 clock source selection"]
#[inline(always)]
pub fn usart3sw(&mut self) -> _USART3SWW {
_USART3SWW { w: self }
}
#[doc = "Bit 8 - Timer1 clock source selection"]
#[inline(always)]
pub fn tim1sw(&mut self) -> _TIM1SWW {
_TIM1SWW { w: self }
}
#[doc = "Bit 9 - Timer8 clock source selection"]
#[inline(always)]
pub fn tim8sw(&mut self) -> _TIM8SWW {
_TIM8SWW { w: self }
}
#[doc = "Bits 20:21 - UART4 clock source selection"]
#[inline(always)]
pub fn uart4sw(&mut self) -> _UART4SWW {
_UART4SWW { w: self }
}
#[doc = "Bits 22:23 - UART5 clock source selection"]
#[inline(always)]
pub fn uart5sw(&mut self) -> _UART5SWW {
_UART5SWW { w: self }
}
#[doc = "Bit 15 - Timer20 clock source selection"]
#[inline(always)]
pub fn tim20sw(&mut self) -> _TIM20SWW {
_TIM20SWW { w: self }
}
#[doc = "Bit 10 - Timer15 clock source selection"]
#[inline(always)]
pub fn tim15sw(&mut self) -> _TIM15SWW {
_TIM15SWW { w: self }
}
#[doc = "Bit 11 - Timer16 clock source selection"]
#[inline(always)]
pub fn tim16sw(&mut self) -> _TIM16SWW {
_TIM16SWW { w: self }
}
#[doc = "Bit 13 - Timer17 clock source selection"]
#[inline(always)]
pub fn tim17sw(&mut self) -> _TIM17SWW {
_TIM17SWW { w: self }
}
#[doc = "Bit 24 - Timer2 clock source selection"]
#[inline(always)]
pub fn tim2sw(&mut self) -> _TIM2SWW {
_TIM2SWW { w: self }
}
#[doc = "Bit 25 - Timer34 clock source selection"]
#[inline(always)]
pub fn tim34sw(&mut self) -> _TIM34SWW {
_TIM34SWW { w: self }
}
}