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#[doc = "Reader of register SMPR1"] pub type R = crate::R<u32, super::SMPR1>; #[doc = "Writer for register SMPR1"] pub type W = crate::W<u32, super::SMPR1>; #[doc = "Register SMPR1 `reset()`'s with value 0"] impl crate::ResetValue for super::SMPR1 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Channel 10 sampling time selection\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum SMP10_A { #[doc = "0: 1.5 ADC clock cycles"] CYCLES1_5 = 0, #[doc = "1: 7.5 ADC clock cycles"] CYCLES7_5 = 1, #[doc = "2: 13.5 ADC clock cycles"] CYCLES13_5 = 2, #[doc = "3: 28.5 ADC clock cycles"] CYCLES28_5 = 3, #[doc = "4: 41.5 ADC clock cycles"] CYCLES41_5 = 4, #[doc = "5: 55.5 ADC clock cycles"] CYCLES55_5 = 5, #[doc = "6: 71.5 ADC clock cycles"] CYCLES71_5 = 6, #[doc = "7: 239.5 ADC clock cycles"] CYCLES239_5 = 7, } impl From<SMP10_A> for u8 { #[inline(always)] fn from(variant: SMP10_A) -> Self { variant as _ } } #[doc = "Reader of field `SMP10`"] pub type SMP10_R = crate::R<u8, SMP10_A>; impl SMP10_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> SMP10_A { match self.bits { 0 => SMP10_A::CYCLES1_5, 1 => SMP10_A::CYCLES7_5, 2 => SMP10_A::CYCLES13_5, 3 => SMP10_A::CYCLES28_5, 4 => SMP10_A::CYCLES41_5, 5 => SMP10_A::CYCLES55_5, 6 => SMP10_A::CYCLES71_5, 7 => SMP10_A::CYCLES239_5, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `CYCLES1_5`"] #[inline(always)] pub fn is_cycles1_5(&self) -> bool { *self == SMP10_A::CYCLES1_5 } #[doc = "Checks if the value of the field is `CYCLES7_5`"] #[inline(always)] pub fn is_cycles7_5(&self) -> bool { *self == SMP10_A::CYCLES7_5 } #[doc = "Checks if the value of the field is `CYCLES13_5`"] #[inline(always)] pub fn is_cycles13_5(&self) -> bool { *self == SMP10_A::CYCLES13_5 } #[doc = "Checks if the value of the field is `CYCLES28_5`"] #[inline(always)] pub fn is_cycles28_5(&self) -> bool { *self == SMP10_A::CYCLES28_5 } #[doc = "Checks if the value of the field is `CYCLES41_5`"] #[inline(always)] pub fn is_cycles41_5(&self) -> bool { *self == SMP10_A::CYCLES41_5 } #[doc = "Checks if the value of the field is `CYCLES55_5`"] #[inline(always)] pub fn is_cycles55_5(&self) -> bool { *self == SMP10_A::CYCLES55_5 } #[doc = "Checks if the value of the field is `CYCLES71_5`"] #[inline(always)] pub fn is_cycles71_5(&self) -> bool { *self == SMP10_A::CYCLES71_5 } #[doc = "Checks if the value of the field is `CYCLES239_5`"] #[inline(always)] pub fn is_cycles239_5(&self) -> bool { *self == SMP10_A::CYCLES239_5 } } #[doc = "Write proxy for field `SMP10`"] pub struct SMP10_W<'a> { w: &'a mut W, } impl<'a> SMP10_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: SMP10_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "1.5 ADC clock cycles"] #[inline(always)] pub fn cycles1_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES1_5) } #[doc = "7.5 ADC clock cycles"] #[inline(always)] pub fn cycles7_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES7_5) } #[doc = "13.5 ADC clock cycles"] #[inline(always)] pub fn cycles13_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES13_5) } #[doc = "28.5 ADC clock cycles"] #[inline(always)] pub fn cycles28_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES28_5) } #[doc = "41.5 ADC clock cycles"] #[inline(always)] pub fn cycles41_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES41_5) } #[doc = "55.5 ADC clock cycles"] #[inline(always)] pub fn cycles55_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES55_5) } #[doc = "71.5 ADC clock cycles"] #[inline(always)] pub fn cycles71_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES71_5) } #[doc = "239.5 ADC clock cycles"] #[inline(always)] pub fn cycles239_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES239_5) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); self.w } } #[doc = "Channel 11 sampling time selection"] pub type SMP11_A = SMP10_A; #[doc = "Reader of field `SMP11`"] pub type SMP11_R = crate::R<u8, SMP10_A>; #[doc = "Write proxy for field `SMP11`"] pub struct SMP11_W<'a> { w: &'a mut W, } impl<'a> SMP11_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: SMP11_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "1.5 ADC clock cycles"] #[inline(always)] pub fn cycles1_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES1_5) } #[doc = "7.5 ADC clock cycles"] #[inline(always)] pub fn cycles7_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES7_5) } #[doc = "13.5 ADC clock cycles"] #[inline(always)] pub fn cycles13_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES13_5) } #[doc = "28.5 ADC clock cycles"] #[inline(always)] pub fn cycles28_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES28_5) } #[doc = "41.5 ADC clock cycles"] #[inline(always)] pub fn cycles41_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES41_5) } #[doc = "55.5 ADC clock cycles"] #[inline(always)] pub fn cycles55_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES55_5) } #[doc = "71.5 ADC clock cycles"] #[inline(always)] pub fn cycles71_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES71_5) } #[doc = "239.5 ADC clock cycles"] #[inline(always)] pub fn cycles239_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES239_5) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 3)) | (((value as u32) & 0x07) << 3); self.w } } #[doc = "Channel 12 sampling time selection"] pub type SMP12_A = SMP10_A; #[doc = "Reader of field `SMP12`"] pub type SMP12_R = crate::R<u8, SMP10_A>; #[doc = "Write proxy for field `SMP12`"] pub struct SMP12_W<'a> { w: &'a mut W, } impl<'a> SMP12_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: SMP12_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "1.5 ADC clock cycles"] #[inline(always)] pub fn cycles1_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES1_5) } #[doc = "7.5 ADC clock cycles"] #[inline(always)] pub fn cycles7_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES7_5) } #[doc = "13.5 ADC clock cycles"] #[inline(always)] pub fn cycles13_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES13_5) } #[doc = "28.5 ADC clock cycles"] #[inline(always)] pub fn cycles28_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES28_5) } #[doc = "41.5 ADC clock cycles"] #[inline(always)] pub fn cycles41_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES41_5) } #[doc = "55.5 ADC clock cycles"] #[inline(always)] pub fn cycles55_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES55_5) } #[doc = "71.5 ADC clock cycles"] #[inline(always)] pub fn cycles71_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES71_5) } #[doc = "239.5 ADC clock cycles"] #[inline(always)] pub fn cycles239_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES239_5) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 6)) | (((value as u32) & 0x07) << 6); self.w } } #[doc = "Channel 13 sampling time selection"] pub type SMP13_A = SMP10_A; #[doc = "Reader of field `SMP13`"] pub type SMP13_R = crate::R<u8, SMP10_A>; #[doc = "Write proxy for field `SMP13`"] pub struct SMP13_W<'a> { w: &'a mut W, } impl<'a> SMP13_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: SMP13_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "1.5 ADC clock cycles"] #[inline(always)] pub fn cycles1_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES1_5) } #[doc = "7.5 ADC clock cycles"] #[inline(always)] pub fn cycles7_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES7_5) } #[doc = "13.5 ADC clock cycles"] #[inline(always)] pub fn cycles13_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES13_5) } #[doc = "28.5 ADC clock cycles"] #[inline(always)] pub fn cycles28_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES28_5) } #[doc = "41.5 ADC clock cycles"] #[inline(always)] pub fn cycles41_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES41_5) } #[doc = "55.5 ADC clock cycles"] #[inline(always)] pub fn cycles55_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES55_5) } #[doc = "71.5 ADC clock cycles"] #[inline(always)] pub fn cycles71_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES71_5) } #[doc = "239.5 ADC clock cycles"] #[inline(always)] pub fn cycles239_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES239_5) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 9)) | (((value as u32) & 0x07) << 9); self.w } } #[doc = "Channel 14 sampling time selection"] pub type SMP14_A = SMP10_A; #[doc = "Reader of field `SMP14`"] pub type SMP14_R = crate::R<u8, SMP10_A>; #[doc = "Write proxy for field `SMP14`"] pub struct SMP14_W<'a> { w: &'a mut W, } impl<'a> SMP14_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: SMP14_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "1.5 ADC clock cycles"] #[inline(always)] pub fn cycles1_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES1_5) } #[doc = "7.5 ADC clock cycles"] #[inline(always)] pub fn cycles7_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES7_5) } #[doc = "13.5 ADC clock cycles"] #[inline(always)] pub fn cycles13_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES13_5) } #[doc = "28.5 ADC clock cycles"] #[inline(always)] pub fn cycles28_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES28_5) } #[doc = "41.5 ADC clock cycles"] #[inline(always)] pub fn cycles41_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES41_5) } #[doc = "55.5 ADC clock cycles"] #[inline(always)] pub fn cycles55_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES55_5) } #[doc = "71.5 ADC clock cycles"] #[inline(always)] pub fn cycles71_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES71_5) } #[doc = "239.5 ADC clock cycles"] #[inline(always)] pub fn cycles239_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES239_5) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12); self.w } } #[doc = "Channel 15 sampling time selection"] pub type SMP15_A = SMP10_A; #[doc = "Reader of field `SMP15`"] pub type SMP15_R = crate::R<u8, SMP10_A>; #[doc = "Write proxy for field `SMP15`"] pub struct SMP15_W<'a> { w: &'a mut W, } impl<'a> SMP15_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: SMP15_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "1.5 ADC clock cycles"] #[inline(always)] pub fn cycles1_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES1_5) } #[doc = "7.5 ADC clock cycles"] #[inline(always)] pub fn cycles7_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES7_5) } #[doc = "13.5 ADC clock cycles"] #[inline(always)] pub fn cycles13_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES13_5) } #[doc = "28.5 ADC clock cycles"] #[inline(always)] pub fn cycles28_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES28_5) } #[doc = "41.5 ADC clock cycles"] #[inline(always)] pub fn cycles41_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES41_5) } #[doc = "55.5 ADC clock cycles"] #[inline(always)] pub fn cycles55_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES55_5) } #[doc = "71.5 ADC clock cycles"] #[inline(always)] pub fn cycles71_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES71_5) } #[doc = "239.5 ADC clock cycles"] #[inline(always)] pub fn cycles239_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES239_5) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 15)) | (((value as u32) & 0x07) << 15); self.w } } #[doc = "Channel 16 sampling time selection"] pub type SMP16_A = SMP10_A; #[doc = "Reader of field `SMP16`"] pub type SMP16_R = crate::R<u8, SMP10_A>; #[doc = "Write proxy for field `SMP16`"] pub struct SMP16_W<'a> { w: &'a mut W, } impl<'a> SMP16_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: SMP16_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "1.5 ADC clock cycles"] #[inline(always)] pub fn cycles1_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES1_5) } #[doc = "7.5 ADC clock cycles"] #[inline(always)] pub fn cycles7_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES7_5) } #[doc = "13.5 ADC clock cycles"] #[inline(always)] pub fn cycles13_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES13_5) } #[doc = "28.5 ADC clock cycles"] #[inline(always)] pub fn cycles28_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES28_5) } #[doc = "41.5 ADC clock cycles"] #[inline(always)] pub fn cycles41_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES41_5) } #[doc = "55.5 ADC clock cycles"] #[inline(always)] pub fn cycles55_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES55_5) } #[doc = "71.5 ADC clock cycles"] #[inline(always)] pub fn cycles71_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES71_5) } #[doc = "239.5 ADC clock cycles"] #[inline(always)] pub fn cycles239_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES239_5) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 18)) | (((value as u32) & 0x07) << 18); self.w } } #[doc = "Channel 17 sampling time selection"] pub type SMP17_A = SMP10_A; #[doc = "Reader of field `SMP17`"] pub type SMP17_R = crate::R<u8, SMP10_A>; #[doc = "Write proxy for field `SMP17`"] pub struct SMP17_W<'a> { w: &'a mut W, } impl<'a> SMP17_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: SMP17_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "1.5 ADC clock cycles"] #[inline(always)] pub fn cycles1_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES1_5) } #[doc = "7.5 ADC clock cycles"] #[inline(always)] pub fn cycles7_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES7_5) } #[doc = "13.5 ADC clock cycles"] #[inline(always)] pub fn cycles13_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES13_5) } #[doc = "28.5 ADC clock cycles"] #[inline(always)] pub fn cycles28_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES28_5) } #[doc = "41.5 ADC clock cycles"] #[inline(always)] pub fn cycles41_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES41_5) } #[doc = "55.5 ADC clock cycles"] #[inline(always)] pub fn cycles55_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES55_5) } #[doc = "71.5 ADC clock cycles"] #[inline(always)] pub fn cycles71_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES71_5) } #[doc = "239.5 ADC clock cycles"] #[inline(always)] pub fn cycles239_5(self) -> &'a mut W { self.variant(SMP10_A::CYCLES239_5) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 21)) | (((value as u32) & 0x07) << 21); self.w } } impl R { #[doc = "Bits 0:2 - Channel 10 sampling time selection"] #[inline(always)] pub fn smp10(&self) -> SMP10_R { SMP10_R::new((self.bits & 0x07) as u8) } #[doc = "Bits 3:5 - Channel 11 sampling time selection"] #[inline(always)] pub fn smp11(&self) -> SMP11_R { SMP11_R::new(((self.bits >> 3) & 0x07) as u8) } #[doc = "Bits 6:8 - Channel 12 sampling time selection"] #[inline(always)] pub fn smp12(&self) -> SMP12_R { SMP12_R::new(((self.bits >> 6) & 0x07) as u8) } #[doc = "Bits 9:11 - Channel 13 sampling time selection"] #[inline(always)] pub fn smp13(&self) -> SMP13_R { SMP13_R::new(((self.bits >> 9) & 0x07) as u8) } #[doc = "Bits 12:14 - Channel 14 sampling time selection"] #[inline(always)] pub fn smp14(&self) -> SMP14_R { SMP14_R::new(((self.bits >> 12) & 0x07) as u8) } #[doc = "Bits 15:17 - Channel 15 sampling time selection"] #[inline(always)] pub fn smp15(&self) -> SMP15_R { SMP15_R::new(((self.bits >> 15) & 0x07) as u8) } #[doc = "Bits 18:20 - Channel 16 sampling time selection"] #[inline(always)] pub fn smp16(&self) -> SMP16_R { SMP16_R::new(((self.bits >> 18) & 0x07) as u8) } #[doc = "Bits 21:23 - Channel 17 sampling time selection"] #[inline(always)] pub fn smp17(&self) -> SMP17_R { SMP17_R::new(((self.bits >> 21) & 0x07) as u8) } } impl W { #[doc = "Bits 0:2 - Channel 10 sampling time selection"] #[inline(always)] pub fn smp10(&mut self) -> SMP10_W { SMP10_W { w: self } } #[doc = "Bits 3:5 - Channel 11 sampling time selection"] #[inline(always)] pub fn smp11(&mut self) -> SMP11_W { SMP11_W { w: self } } #[doc = "Bits 6:8 - Channel 12 sampling time selection"] #[inline(always)] pub fn smp12(&mut self) -> SMP12_W { SMP12_W { w: self } } #[doc = "Bits 9:11 - Channel 13 sampling time selection"] #[inline(always)] pub fn smp13(&mut self) -> SMP13_W { SMP13_W { w: self } } #[doc = "Bits 12:14 - Channel 14 sampling time selection"] #[inline(always)] pub fn smp14(&mut self) -> SMP14_W { SMP14_W { w: self } } #[doc = "Bits 15:17 - Channel 15 sampling time selection"] #[inline(always)] pub fn smp15(&mut self) -> SMP15_W { SMP15_W { w: self } } #[doc = "Bits 18:20 - Channel 16 sampling time selection"] #[inline(always)] pub fn smp16(&mut self) -> SMP16_W { SMP16_W { w: self } } #[doc = "Bits 21:23 - Channel 17 sampling time selection"] #[inline(always)] pub fn smp17(&mut self) -> SMP17_W { SMP17_W { w: self } } }