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#[doc = "Reader of register CFGR1"] pub type R = crate::R<u32, super::CFGR1>; #[doc = "Writer for register CFGR1"] pub type W = crate::W<u32, super::CFGR1>; #[doc = "Register CFGR1 `reset()`'s with value 0"] impl crate::ResetValue for super::CFGR1 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `MEM_MODE`"] pub type MEM_MODE_R = crate::R<u8, u8>; #[doc = "Write proxy for field `MEM_MODE`"] pub struct MEM_MODE_W<'a> { w: &'a mut W, } impl<'a> MEM_MODE_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); self.w } } #[doc = "Reader of field `USB_IT_RMP`"] pub type USB_IT_RMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `USB_IT_RMP`"] pub struct USB_IT_RMP_W<'a> { w: &'a mut W, } impl<'a> USB_IT_RMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); self.w } } #[doc = "Reader of field `TIM1_ITR3_RMP`"] pub type TIM1_ITR3_RMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TIM1_ITR3_RMP`"] pub struct TIM1_ITR3_RMP_W<'a> { w: &'a mut W, } impl<'a> TIM1_ITR3_RMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); self.w } } #[doc = "Reader of field `DAC_TRIG_RMP`"] pub type DAC_TRIG_RMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DAC_TRIG_RMP`"] pub struct DAC_TRIG_RMP_W<'a> { w: &'a mut W, } impl<'a> DAC_TRIG_RMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); self.w } } #[doc = "Reader of field `ADC24_DMA_RMP`"] pub type ADC24_DMA_RMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ADC24_DMA_RMP`"] pub struct ADC24_DMA_RMP_W<'a> { w: &'a mut W, } impl<'a> ADC24_DMA_RMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "Reader of field `TIM16_DMA_RMP`"] pub type TIM16_DMA_RMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TIM16_DMA_RMP`"] pub struct TIM16_DMA_RMP_W<'a> { w: &'a mut W, } impl<'a> TIM16_DMA_RMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); self.w } } #[doc = "Reader of field `TIM17_DMA_RMP`"] pub type TIM17_DMA_RMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TIM17_DMA_RMP`"] pub struct TIM17_DMA_RMP_W<'a> { w: &'a mut W, } impl<'a> TIM17_DMA_RMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); self.w } } #[doc = "Reader of field `TIM6_DAC1_DMA_RMP`"] pub type TIM6_DAC1_DMA_RMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TIM6_DAC1_DMA_RMP`"] pub struct TIM6_DAC1_DMA_RMP_W<'a> { w: &'a mut W, } impl<'a> TIM6_DAC1_DMA_RMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); self.w } } #[doc = "Reader of field `TIM7_DAC2_DMA_RMP`"] pub type TIM7_DAC2_DMA_RMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TIM7_DAC2_DMA_RMP`"] pub struct TIM7_DAC2_DMA_RMP_W<'a> { w: &'a mut W, } impl<'a> TIM7_DAC2_DMA_RMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); self.w } } #[doc = "Reader of field `I2C_PB6_FMP`"] pub type I2C_PB6_FMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `I2C_PB6_FMP`"] pub struct I2C_PB6_FMP_W<'a> { w: &'a mut W, } impl<'a> I2C_PB6_FMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); self.w } } #[doc = "Reader of field `I2C_PB7_FMP`"] pub type I2C_PB7_FMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `I2C_PB7_FMP`"] pub struct I2C_PB7_FMP_W<'a> { w: &'a mut W, } impl<'a> I2C_PB7_FMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); self.w } } #[doc = "Reader of field `I2C_PB8_FMP`"] pub type I2C_PB8_FMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `I2C_PB8_FMP`"] pub struct I2C_PB8_FMP_W<'a> { w: &'a mut W, } impl<'a> I2C_PB8_FMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18); self.w } } #[doc = "Reader of field `I2C_PB9_FMP`"] pub type I2C_PB9_FMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `I2C_PB9_FMP`"] pub struct I2C_PB9_FMP_W<'a> { w: &'a mut W, } impl<'a> I2C_PB9_FMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); self.w } } #[doc = "Reader of field `I2C1_FMP`"] pub type I2C1_FMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `I2C1_FMP`"] pub struct I2C1_FMP_W<'a> { w: &'a mut W, } impl<'a> I2C1_FMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); self.w } } #[doc = "Reader of field `I2C2_FMP`"] pub type I2C2_FMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `I2C2_FMP`"] pub struct I2C2_FMP_W<'a> { w: &'a mut W, } impl<'a> I2C2_FMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); self.w } } #[doc = "Reader of field `ENCODER_MODE`"] pub type ENCODER_MODE_R = crate::R<u8, u8>; #[doc = "Write proxy for field `ENCODER_MODE`"] pub struct ENCODER_MODE_W<'a> { w: &'a mut W, } impl<'a> ENCODER_MODE_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22); self.w } } #[doc = "Reader of field `FPU_IE`"] pub type FPU_IE_R = crate::R<u8, u8>; #[doc = "Write proxy for field `FPU_IE`"] pub struct FPU_IE_W<'a> { w: &'a mut W, } impl<'a> FPU_IE_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x3f << 26)) | (((value as u32) & 0x3f) << 26); self.w } } #[doc = "Reader of field `DAC2_CH1_DMA_RMP`"] pub type DAC2_CH1_DMA_RMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DAC2_CH1_DMA_RMP`"] pub struct DAC2_CH1_DMA_RMP_W<'a> { w: &'a mut W, } impl<'a> DAC2_CH1_DMA_RMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); self.w } } #[doc = "Reader of field `I2C3_FMP`"] pub type I2C3_FMP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `I2C3_FMP`"] pub struct I2C3_FMP_W<'a> { w: &'a mut W, } impl<'a> I2C3_FMP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); self.w } } impl R { #[doc = "Bits 0:2 - Memory mapping selection bits"] #[inline(always)] pub fn mem_mode(&self) -> MEM_MODE_R { MEM_MODE_R::new((self.bits & 0x07) as u8) } #[doc = "Bit 5 - USB interrupt remap"] #[inline(always)] pub fn usb_it_rmp(&self) -> USB_IT_RMP_R { USB_IT_RMP_R::new(((self.bits >> 5) & 0x01) != 0) } #[doc = "Bit 6 - Timer 1 ITR3 selection"] #[inline(always)] pub fn tim1_itr3_rmp(&self) -> TIM1_ITR3_RMP_R { TIM1_ITR3_RMP_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bit 7 - DAC trigger remap (when TSEL = 001)"] #[inline(always)] pub fn dac_trig_rmp(&self) -> DAC_TRIG_RMP_R { DAC_TRIG_RMP_R::new(((self.bits >> 7) & 0x01) != 0) } #[doc = "Bit 8 - ADC24 DMA remapping bit"] #[inline(always)] pub fn adc24_dma_rmp(&self) -> ADC24_DMA_RMP_R { ADC24_DMA_RMP_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bit 11 - TIM16 DMA request remapping bit"] #[inline(always)] pub fn tim16_dma_rmp(&self) -> TIM16_DMA_RMP_R { TIM16_DMA_RMP_R::new(((self.bits >> 11) & 0x01) != 0) } #[doc = "Bit 12 - TIM17 DMA request remapping bit"] #[inline(always)] pub fn tim17_dma_rmp(&self) -> TIM17_DMA_RMP_R { TIM17_DMA_RMP_R::new(((self.bits >> 12) & 0x01) != 0) } #[doc = "Bit 13 - TIM6 and DAC1 DMA request remapping bit"] #[inline(always)] pub fn tim6_dac1_dma_rmp(&self) -> TIM6_DAC1_DMA_RMP_R { TIM6_DAC1_DMA_RMP_R::new(((self.bits >> 13) & 0x01) != 0) } #[doc = "Bit 14 - TIM7 and DAC2 DMA request remapping bit"] #[inline(always)] pub fn tim7_dac2_dma_rmp(&self) -> TIM7_DAC2_DMA_RMP_R { TIM7_DAC2_DMA_RMP_R::new(((self.bits >> 14) & 0x01) != 0) } #[doc = "Bit 16 - Fast Mode Plus (FM+) driving capability activation bits."] #[inline(always)] pub fn i2c_pb6_fmp(&self) -> I2C_PB6_FMP_R { I2C_PB6_FMP_R::new(((self.bits >> 16) & 0x01) != 0) } #[doc = "Bit 17 - Fast Mode Plus (FM+) driving capability activation bits."] #[inline(always)] pub fn i2c_pb7_fmp(&self) -> I2C_PB7_FMP_R { I2C_PB7_FMP_R::new(((self.bits >> 17) & 0x01) != 0) } #[doc = "Bit 18 - Fast Mode Plus (FM+) driving capability activation bits."] #[inline(always)] pub fn i2c_pb8_fmp(&self) -> I2C_PB8_FMP_R { I2C_PB8_FMP_R::new(((self.bits >> 18) & 0x01) != 0) } #[doc = "Bit 19 - Fast Mode Plus (FM+) driving capability activation bits."] #[inline(always)] pub fn i2c_pb9_fmp(&self) -> I2C_PB9_FMP_R { I2C_PB9_FMP_R::new(((self.bits >> 19) & 0x01) != 0) } #[doc = "Bit 20 - I2C1 Fast Mode Plus"] #[inline(always)] pub fn i2c1_fmp(&self) -> I2C1_FMP_R { I2C1_FMP_R::new(((self.bits >> 20) & 0x01) != 0) } #[doc = "Bit 21 - I2C2 Fast Mode Plus"] #[inline(always)] pub fn i2c2_fmp(&self) -> I2C2_FMP_R { I2C2_FMP_R::new(((self.bits >> 21) & 0x01) != 0) } #[doc = "Bits 22:23 - Encoder mode"] #[inline(always)] pub fn encoder_mode(&self) -> ENCODER_MODE_R { ENCODER_MODE_R::new(((self.bits >> 22) & 0x03) as u8) } #[doc = "Bits 26:31 - Interrupt enable bits from FPU"] #[inline(always)] pub fn fpu_ie(&self) -> FPU_IE_R { FPU_IE_R::new(((self.bits >> 26) & 0x3f) as u8) } #[doc = "Bit 15 - DAC2 channel1 DMA remap"] #[inline(always)] pub fn dac2_ch1_dma_rmp(&self) -> DAC2_CH1_DMA_RMP_R { DAC2_CH1_DMA_RMP_R::new(((self.bits >> 15) & 0x01) != 0) } #[doc = "Bit 24 - I2C3 Fast Mode Plus"] #[inline(always)] pub fn i2c3_fmp(&self) -> I2C3_FMP_R { I2C3_FMP_R::new(((self.bits >> 24) & 0x01) != 0) } } impl W { #[doc = "Bits 0:2 - Memory mapping selection bits"] #[inline(always)] pub fn mem_mode(&mut self) -> MEM_MODE_W { MEM_MODE_W { w: self } } #[doc = "Bit 5 - USB interrupt remap"] #[inline(always)] pub fn usb_it_rmp(&mut self) -> USB_IT_RMP_W { USB_IT_RMP_W { w: self } } #[doc = "Bit 6 - Timer 1 ITR3 selection"] #[inline(always)] pub fn tim1_itr3_rmp(&mut self) -> TIM1_ITR3_RMP_W { TIM1_ITR3_RMP_W { w: self } } #[doc = "Bit 7 - DAC trigger remap (when TSEL = 001)"] #[inline(always)] pub fn dac_trig_rmp(&mut self) -> DAC_TRIG_RMP_W { DAC_TRIG_RMP_W { w: self } } #[doc = "Bit 8 - ADC24 DMA remapping bit"] #[inline(always)] pub fn adc24_dma_rmp(&mut self) -> ADC24_DMA_RMP_W { ADC24_DMA_RMP_W { w: self } } #[doc = "Bit 11 - TIM16 DMA request remapping bit"] #[inline(always)] pub fn tim16_dma_rmp(&mut self) -> TIM16_DMA_RMP_W { TIM16_DMA_RMP_W { w: self } } #[doc = "Bit 12 - TIM17 DMA request remapping bit"] #[inline(always)] pub fn tim17_dma_rmp(&mut self) -> TIM17_DMA_RMP_W { TIM17_DMA_RMP_W { w: self } } #[doc = "Bit 13 - TIM6 and DAC1 DMA request remapping bit"] #[inline(always)] pub fn tim6_dac1_dma_rmp(&mut self) -> TIM6_DAC1_DMA_RMP_W { TIM6_DAC1_DMA_RMP_W { w: self } } #[doc = "Bit 14 - TIM7 and DAC2 DMA request remapping bit"] #[inline(always)] pub fn tim7_dac2_dma_rmp(&mut self) -> TIM7_DAC2_DMA_RMP_W { TIM7_DAC2_DMA_RMP_W { w: self } } #[doc = "Bit 16 - Fast Mode Plus (FM+) driving capability activation bits."] #[inline(always)] pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W { I2C_PB6_FMP_W { w: self } } #[doc = "Bit 17 - Fast Mode Plus (FM+) driving capability activation bits."] #[inline(always)] pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W { I2C_PB7_FMP_W { w: self } } #[doc = "Bit 18 - Fast Mode Plus (FM+) driving capability activation bits."] #[inline(always)] pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W { I2C_PB8_FMP_W { w: self } } #[doc = "Bit 19 - Fast Mode Plus (FM+) driving capability activation bits."] #[inline(always)] pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W { I2C_PB9_FMP_W { w: self } } #[doc = "Bit 20 - I2C1 Fast Mode Plus"] #[inline(always)] pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W { I2C1_FMP_W { w: self } } #[doc = "Bit 21 - I2C2 Fast Mode Plus"] #[inline(always)] pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W { I2C2_FMP_W { w: self } } #[doc = "Bits 22:23 - Encoder mode"] #[inline(always)] pub fn encoder_mode(&mut self) -> ENCODER_MODE_W { ENCODER_MODE_W { w: self } } #[doc = "Bits 26:31 - Interrupt enable bits from FPU"] #[inline(always)] pub fn fpu_ie(&mut self) -> FPU_IE_W { FPU_IE_W { w: self } } #[doc = "Bit 15 - DAC2 channel1 DMA remap"] #[inline(always)] pub fn dac2_ch1_dma_rmp(&mut self) -> DAC2_CH1_DMA_RMP_W { DAC2_CH1_DMA_RMP_W { w: self } } #[doc = "Bit 24 - I2C3 Fast Mode Plus"] #[inline(always)] pub fn i2c3_fmp(&mut self) -> I2C3_FMP_W { I2C3_FMP_W { w: self } } }