[−][src]Struct stm32f1xx_hal::pac::dac::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub cr: Reg<u32, _CR>,
    pub swtrigr: Reg<u32, _SWTRIGR>,
    pub dhr12r1: Reg<u32, _DHR12R1>,
    pub dhr12l1: Reg<u32, _DHR12L1>,
    pub dhr8r1: Reg<u32, _DHR8R1>,
    pub dhr12r2: Reg<u32, _DHR12R2>,
    pub dhr12l2: Reg<u32, _DHR12L2>,
    pub dhr8r2: Reg<u32, _DHR8R2>,
    pub dhr12rd: Reg<u32, _DHR12RD>,
    pub dhr12ld: Reg<u32, _DHR12LD>,
    pub dhr8rd: Reg<u32, _DHR8RD>,
    pub dor1: Reg<u32, _DOR1>,
    pub dor2: Reg<u32, _DOR2>,
}

Register block

Fields

cr: Reg<u32, _CR>

0x00 - Control register (DAC_CR)

swtrigr: Reg<u32, _SWTRIGR>

0x04 - DAC software trigger register (DAC_SWTRIGR)

dhr12r1: Reg<u32, _DHR12R1>

0x08 - DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)

dhr12l1: Reg<u32, _DHR12L1>

0x0c - DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)

dhr8r1: Reg<u32, _DHR8R1>

0x10 - DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)

dhr12r2: Reg<u32, _DHR12R2>

0x14 - DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)

dhr12l2: Reg<u32, _DHR12L2>

0x18 - DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)

dhr8r2: Reg<u32, _DHR8R2>

0x1c - DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)

dhr12rd: Reg<u32, _DHR12RD>

0x20 - Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved

dhr12ld: Reg<u32, _DHR12LD>

0x24 - DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved

dhr8rd: Reg<u32, _DHR8RD>

0x28 - DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved

dor1: Reg<u32, _DOR1>

0x2c - DAC channel1 data output register (DAC_DOR1)

dor2: Reg<u32, _DOR2>

0x30 - DAC channel2 data output register (DAC_DOR2)

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