1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
#[doc = "Register `DCR` reader"]
pub struct R(crate::R<DCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DCR` writer"]
pub struct W(crate::W<DCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DBL` reader - DMA burst length"]
pub struct DBL_R(crate::FieldReader<u8, u8>);
impl DBL_R {
pub(crate) fn new(bits: u8) -> Self {
DBL_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for DBL_R {
type Target = crate::FieldReader<u8, u8>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `DBL` writer - DMA burst length"]
pub struct DBL_W<'a> {
w: &'a mut W,
}
impl<'a> DBL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8);
self.w
}
}
#[doc = "Field `DBA` reader - DMA base address"]
pub struct DBA_R(crate::FieldReader<u8, u8>);
impl DBA_R {
pub(crate) fn new(bits: u8) -> Self {
DBA_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for DBA_R {
type Target = crate::FieldReader<u8, u8>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `DBA` writer - DMA base address"]
pub struct DBA_W<'a> {
w: &'a mut W,
}
impl<'a> DBA_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f);
self.w
}
}
impl R {
#[doc = "Bits 8:12 - DMA burst length"]
#[inline(always)]
pub fn dbl(&self) -> DBL_R {
DBL_R::new(((self.bits >> 8) & 0x1f) as u8)
}
#[doc = "Bits 0:4 - DMA base address"]
#[inline(always)]
pub fn dba(&self) -> DBA_R {
DBA_R::new((self.bits & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 8:12 - DMA burst length"]
#[inline(always)]
pub fn dbl(&mut self) -> DBL_W {
DBL_W { w: self }
}
#[doc = "Bits 0:4 - DMA base address"]
#[inline(always)]
pub fn dba(&mut self) -> DBA_W {
DBA_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcr](index.html) module"]
pub struct DCR_SPEC;
impl crate::RegisterSpec for DCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dcr::R](R) reader structure"]
impl crate::Readable for DCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dcr::W](W) writer structure"]
impl crate::Writable for DCR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets DCR to value 0"]
impl crate::Resettable for DCR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}