stm32f1_staging/stm32f107/rtc/
prll.rs

1///Register `PRLL` writer
2pub type W = crate::W<PRLLrs>;
3///Field `PRLL` writer - RTC Prescaler Divider Register Low
4pub type PRLL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16, crate::Safe>;
5impl core::fmt::Debug for crate::generic::Reg<PRLLrs> {
6    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
7        write!(f, "(not readable)")
8    }
9}
10impl W {
11    ///Bits 0:15 - RTC Prescaler Divider Register Low
12    #[inline(always)]
13    pub fn prll(&mut self) -> PRLL_W<PRLLrs> {
14        PRLL_W::new(self, 0)
15    }
16}
17/**RTC Prescaler Load Register Low
18
19You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prll::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
20
21See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RTC:PRLL)*/
22pub struct PRLLrs;
23impl crate::RegisterSpec for PRLLrs {
24    type Ux = u32;
25}
26///`write(|w| ..)` method takes [`prll::W`](W) writer structure
27impl crate::Writable for PRLLrs {
28    type Safety = crate::Unsafe;
29}
30///`reset()` method sets PRLL to value 0x8000
31impl crate::Resettable for PRLLrs {
32    const RESET_VALUE: u32 = 0x8000;
33}
stm32f1_staging/stm32f107/rtc/prll.rs

stm32f1_staging/stm32f107/rtc/
prll.rs
