stm32f1_staging/stm32f107/exti/
imr.rs

1///Register `IMR` reader
2pub type R = crate::R<IMRrs>;
3///Register `IMR` writer
4pub type W = crate::W<IMRrs>;
5/**Interrupt Mask on line %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum INTERRUPT_MASK {
11    ///0: Interrupt request line is masked
12    Masked = 0,
13    ///1: Interrupt request line is unmasked
14    Unmasked = 1,
15}
16impl From<INTERRUPT_MASK> for bool {
17    #[inline(always)]
18    fn from(variant: INTERRUPT_MASK) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `MR(0-19)` reader - Interrupt Mask on line %s
23pub type MR_R = crate::BitReader<INTERRUPT_MASK>;
24impl MR_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> INTERRUPT_MASK {
28        match self.bits {
29            false => INTERRUPT_MASK::Masked,
30            true => INTERRUPT_MASK::Unmasked,
31        }
32    }
33    ///Interrupt request line is masked
34    #[inline(always)]
35    pub fn is_masked(&self) -> bool {
36        *self == INTERRUPT_MASK::Masked
37    }
38    ///Interrupt request line is unmasked
39    #[inline(always)]
40    pub fn is_unmasked(&self) -> bool {
41        *self == INTERRUPT_MASK::Unmasked
42    }
43}
44///Field `MR(0-19)` writer - Interrupt Mask on line %s
45pub type MR_W<'a, REG> = crate::BitWriter<'a, REG, INTERRUPT_MASK>;
46impl<'a, REG> MR_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Interrupt request line is masked
51    #[inline(always)]
52    pub fn masked(self) -> &'a mut crate::W<REG> {
53        self.variant(INTERRUPT_MASK::Masked)
54    }
55    ///Interrupt request line is unmasked
56    #[inline(always)]
57    pub fn unmasked(self) -> &'a mut crate::W<REG> {
58        self.variant(INTERRUPT_MASK::Unmasked)
59    }
60}
61impl R {
62    ///Interrupt Mask on line (0-19)
63    ///
64    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MR0` field.</div>
65    #[inline(always)]
66    pub fn mr(&self, n: u8) -> MR_R {
67        #[allow(clippy::no_effect)] [(); 20][n as usize];
68        MR_R::new(((self.bits >> n) & 1) != 0)
69    }
70    ///Iterator for array of:
71    ///Interrupt Mask on line (0-19)
72    #[inline(always)]
73    pub fn mr_iter(&self) -> impl Iterator<Item = MR_R> + '_ {
74        (0..20).map(move |n| MR_R::new(((self.bits >> n) & 1) != 0))
75    }
76    ///Bit 0 - Interrupt Mask on line 0
77    #[inline(always)]
78    pub fn mr0(&self) -> MR_R {
79        MR_R::new((self.bits & 1) != 0)
80    }
81    ///Bit 1 - Interrupt Mask on line 1
82    #[inline(always)]
83    pub fn mr1(&self) -> MR_R {
84        MR_R::new(((self.bits >> 1) & 1) != 0)
85    }
86    ///Bit 2 - Interrupt Mask on line 2
87    #[inline(always)]
88    pub fn mr2(&self) -> MR_R {
89        MR_R::new(((self.bits >> 2) & 1) != 0)
90    }
91    ///Bit 3 - Interrupt Mask on line 3
92    #[inline(always)]
93    pub fn mr3(&self) -> MR_R {
94        MR_R::new(((self.bits >> 3) & 1) != 0)
95    }
96    ///Bit 4 - Interrupt Mask on line 4
97    #[inline(always)]
98    pub fn mr4(&self) -> MR_R {
99        MR_R::new(((self.bits >> 4) & 1) != 0)
100    }
101    ///Bit 5 - Interrupt Mask on line 5
102    #[inline(always)]
103    pub fn mr5(&self) -> MR_R {
104        MR_R::new(((self.bits >> 5) & 1) != 0)
105    }
106    ///Bit 6 - Interrupt Mask on line 6
107    #[inline(always)]
108    pub fn mr6(&self) -> MR_R {
109        MR_R::new(((self.bits >> 6) & 1) != 0)
110    }
111    ///Bit 7 - Interrupt Mask on line 7
112    #[inline(always)]
113    pub fn mr7(&self) -> MR_R {
114        MR_R::new(((self.bits >> 7) & 1) != 0)
115    }
116    ///Bit 8 - Interrupt Mask on line 8
117    #[inline(always)]
118    pub fn mr8(&self) -> MR_R {
119        MR_R::new(((self.bits >> 8) & 1) != 0)
120    }
121    ///Bit 9 - Interrupt Mask on line 9
122    #[inline(always)]
123    pub fn mr9(&self) -> MR_R {
124        MR_R::new(((self.bits >> 9) & 1) != 0)
125    }
126    ///Bit 10 - Interrupt Mask on line 10
127    #[inline(always)]
128    pub fn mr10(&self) -> MR_R {
129        MR_R::new(((self.bits >> 10) & 1) != 0)
130    }
131    ///Bit 11 - Interrupt Mask on line 11
132    #[inline(always)]
133    pub fn mr11(&self) -> MR_R {
134        MR_R::new(((self.bits >> 11) & 1) != 0)
135    }
136    ///Bit 12 - Interrupt Mask on line 12
137    #[inline(always)]
138    pub fn mr12(&self) -> MR_R {
139        MR_R::new(((self.bits >> 12) & 1) != 0)
140    }
141    ///Bit 13 - Interrupt Mask on line 13
142    #[inline(always)]
143    pub fn mr13(&self) -> MR_R {
144        MR_R::new(((self.bits >> 13) & 1) != 0)
145    }
146    ///Bit 14 - Interrupt Mask on line 14
147    #[inline(always)]
148    pub fn mr14(&self) -> MR_R {
149        MR_R::new(((self.bits >> 14) & 1) != 0)
150    }
151    ///Bit 15 - Interrupt Mask on line 15
152    #[inline(always)]
153    pub fn mr15(&self) -> MR_R {
154        MR_R::new(((self.bits >> 15) & 1) != 0)
155    }
156    ///Bit 16 - Interrupt Mask on line 16
157    #[inline(always)]
158    pub fn mr16(&self) -> MR_R {
159        MR_R::new(((self.bits >> 16) & 1) != 0)
160    }
161    ///Bit 17 - Interrupt Mask on line 17
162    #[inline(always)]
163    pub fn mr17(&self) -> MR_R {
164        MR_R::new(((self.bits >> 17) & 1) != 0)
165    }
166    ///Bit 18 - Interrupt Mask on line 18
167    #[inline(always)]
168    pub fn mr18(&self) -> MR_R {
169        MR_R::new(((self.bits >> 18) & 1) != 0)
170    }
171    ///Bit 19 - Interrupt Mask on line 19
172    #[inline(always)]
173    pub fn mr19(&self) -> MR_R {
174        MR_R::new(((self.bits >> 19) & 1) != 0)
175    }
176}
177impl core::fmt::Debug for R {
178    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
179        f.debug_struct("IMR")
180            .field("mr0", &self.mr0())
181            .field("mr1", &self.mr1())
182            .field("mr2", &self.mr2())
183            .field("mr3", &self.mr3())
184            .field("mr4", &self.mr4())
185            .field("mr5", &self.mr5())
186            .field("mr6", &self.mr6())
187            .field("mr7", &self.mr7())
188            .field("mr8", &self.mr8())
189            .field("mr9", &self.mr9())
190            .field("mr10", &self.mr10())
191            .field("mr11", &self.mr11())
192            .field("mr12", &self.mr12())
193            .field("mr13", &self.mr13())
194            .field("mr14", &self.mr14())
195            .field("mr15", &self.mr15())
196            .field("mr16", &self.mr16())
197            .field("mr17", &self.mr17())
198            .field("mr18", &self.mr18())
199            .field("mr19", &self.mr19())
200            .finish()
201    }
202}
203impl W {
204    ///Interrupt Mask on line (0-19)
205    ///
206    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MR0` field.</div>
207    #[inline(always)]
208    pub fn mr(&mut self, n: u8) -> MR_W<IMRrs> {
209        #[allow(clippy::no_effect)] [(); 20][n as usize];
210        MR_W::new(self, n)
211    }
212    ///Bit 0 - Interrupt Mask on line 0
213    #[inline(always)]
214    pub fn mr0(&mut self) -> MR_W<IMRrs> {
215        MR_W::new(self, 0)
216    }
217    ///Bit 1 - Interrupt Mask on line 1
218    #[inline(always)]
219    pub fn mr1(&mut self) -> MR_W<IMRrs> {
220        MR_W::new(self, 1)
221    }
222    ///Bit 2 - Interrupt Mask on line 2
223    #[inline(always)]
224    pub fn mr2(&mut self) -> MR_W<IMRrs> {
225        MR_W::new(self, 2)
226    }
227    ///Bit 3 - Interrupt Mask on line 3
228    #[inline(always)]
229    pub fn mr3(&mut self) -> MR_W<IMRrs> {
230        MR_W::new(self, 3)
231    }
232    ///Bit 4 - Interrupt Mask on line 4
233    #[inline(always)]
234    pub fn mr4(&mut self) -> MR_W<IMRrs> {
235        MR_W::new(self, 4)
236    }
237    ///Bit 5 - Interrupt Mask on line 5
238    #[inline(always)]
239    pub fn mr5(&mut self) -> MR_W<IMRrs> {
240        MR_W::new(self, 5)
241    }
242    ///Bit 6 - Interrupt Mask on line 6
243    #[inline(always)]
244    pub fn mr6(&mut self) -> MR_W<IMRrs> {
245        MR_W::new(self, 6)
246    }
247    ///Bit 7 - Interrupt Mask on line 7
248    #[inline(always)]
249    pub fn mr7(&mut self) -> MR_W<IMRrs> {
250        MR_W::new(self, 7)
251    }
252    ///Bit 8 - Interrupt Mask on line 8
253    #[inline(always)]
254    pub fn mr8(&mut self) -> MR_W<IMRrs> {
255        MR_W::new(self, 8)
256    }
257    ///Bit 9 - Interrupt Mask on line 9
258    #[inline(always)]
259    pub fn mr9(&mut self) -> MR_W<IMRrs> {
260        MR_W::new(self, 9)
261    }
262    ///Bit 10 - Interrupt Mask on line 10
263    #[inline(always)]
264    pub fn mr10(&mut self) -> MR_W<IMRrs> {
265        MR_W::new(self, 10)
266    }
267    ///Bit 11 - Interrupt Mask on line 11
268    #[inline(always)]
269    pub fn mr11(&mut self) -> MR_W<IMRrs> {
270        MR_W::new(self, 11)
271    }
272    ///Bit 12 - Interrupt Mask on line 12
273    #[inline(always)]
274    pub fn mr12(&mut self) -> MR_W<IMRrs> {
275        MR_W::new(self, 12)
276    }
277    ///Bit 13 - Interrupt Mask on line 13
278    #[inline(always)]
279    pub fn mr13(&mut self) -> MR_W<IMRrs> {
280        MR_W::new(self, 13)
281    }
282    ///Bit 14 - Interrupt Mask on line 14
283    #[inline(always)]
284    pub fn mr14(&mut self) -> MR_W<IMRrs> {
285        MR_W::new(self, 14)
286    }
287    ///Bit 15 - Interrupt Mask on line 15
288    #[inline(always)]
289    pub fn mr15(&mut self) -> MR_W<IMRrs> {
290        MR_W::new(self, 15)
291    }
292    ///Bit 16 - Interrupt Mask on line 16
293    #[inline(always)]
294    pub fn mr16(&mut self) -> MR_W<IMRrs> {
295        MR_W::new(self, 16)
296    }
297    ///Bit 17 - Interrupt Mask on line 17
298    #[inline(always)]
299    pub fn mr17(&mut self) -> MR_W<IMRrs> {
300        MR_W::new(self, 17)
301    }
302    ///Bit 18 - Interrupt Mask on line 18
303    #[inline(always)]
304    pub fn mr18(&mut self) -> MR_W<IMRrs> {
305        MR_W::new(self, 18)
306    }
307    ///Bit 19 - Interrupt Mask on line 19
308    #[inline(always)]
309    pub fn mr19(&mut self) -> MR_W<IMRrs> {
310        MR_W::new(self, 19)
311    }
312}
313/**Interrupt mask register (EXTI_IMR)
314
315You can [`read`](crate::Reg::read) this register and get [`imr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
316
317See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#EXTI:IMR)*/
318pub struct IMRrs;
319impl crate::RegisterSpec for IMRrs {
320    type Ux = u32;
321}
322///`read()` method returns [`imr::R`](R) reader structure
323impl crate::Readable for IMRrs {}
324///`write(|w| ..)` method takes [`imr::W`](W) writer structure
325impl crate::Writable for IMRrs {
326    type Safety = crate::Unsafe;
327}
328///`reset()` method sets IMR to value 0
329impl crate::Resettable for IMRrs {}
stm32f1_staging/stm32f107/exti/imr.rs

stm32f1_staging/stm32f107/exti/
imr.rs
