stm32f1_staging/stm32f103/gpioa/
crl.rs

1///Register `CRL` reader
2pub type R = crate::R<CRLrs>;
3///Register `CRL` writer
4pub type W = crate::W<CRLrs>;
5/**Port n.%s mode bits
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum MODE {
12    ///0: Input mode (reset state)
13    Input = 0,
14    ///1: Output mode 10 MHz
15    Output = 1,
16    ///2: Output mode 2 MHz
17    Output2 = 2,
18    ///3: Output mode 50 MHz
19    Output50 = 3,
20}
21impl From<MODE> for u8 {
22    #[inline(always)]
23    fn from(variant: MODE) -> Self {
24        variant as _
25    }
26}
27impl crate::FieldSpec for MODE {
28    type Ux = u8;
29}
30impl crate::IsEnum for MODE {}
31///Field `MODE(0-7)` reader - Port n.%s mode bits
32pub type MODE_R = crate::FieldReader<MODE>;
33impl MODE_R {
34    ///Get enumerated values variant
35    #[inline(always)]
36    pub const fn variant(&self) -> MODE {
37        match self.bits {
38            0 => MODE::Input,
39            1 => MODE::Output,
40            2 => MODE::Output2,
41            3 => MODE::Output50,
42            _ => unreachable!(),
43        }
44    }
45    ///Input mode (reset state)
46    #[inline(always)]
47    pub fn is_input(&self) -> bool {
48        *self == MODE::Input
49    }
50    ///Output mode 10 MHz
51    #[inline(always)]
52    pub fn is_output(&self) -> bool {
53        *self == MODE::Output
54    }
55    ///Output mode 2 MHz
56    #[inline(always)]
57    pub fn is_output2(&self) -> bool {
58        *self == MODE::Output2
59    }
60    ///Output mode 50 MHz
61    #[inline(always)]
62    pub fn is_output50(&self) -> bool {
63        *self == MODE::Output50
64    }
65}
66///Field `MODE(0-7)` writer - Port n.%s mode bits
67pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, MODE, crate::Safe>;
68impl<'a, REG> MODE_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    ///Input mode (reset state)
74    #[inline(always)]
75    pub fn input(self) -> &'a mut crate::W<REG> {
76        self.variant(MODE::Input)
77    }
78    ///Output mode 10 MHz
79    #[inline(always)]
80    pub fn output(self) -> &'a mut crate::W<REG> {
81        self.variant(MODE::Output)
82    }
83    ///Output mode 2 MHz
84    #[inline(always)]
85    pub fn output2(self) -> &'a mut crate::W<REG> {
86        self.variant(MODE::Output2)
87    }
88    ///Output mode 50 MHz
89    #[inline(always)]
90    pub fn output50(self) -> &'a mut crate::W<REG> {
91        self.variant(MODE::Output50)
92    }
93}
94/**Port n.%s configuration bits
95
96Value on reset: 1*/
97#[cfg_attr(feature = "defmt", derive(defmt::Format))]
98#[derive(Clone, Copy, Debug, PartialEq, Eq)]
99#[repr(u8)]
100pub enum CONFIG {
101    ///0: Analog mode / Push-Pull mode
102    PushPull = 0,
103    ///1: Floating input (reset state) / Open Drain-Mode
104    OpenDrain = 1,
105    ///2: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
106    AltPushPull = 2,
107    ///3: Alternate Function Open-Drain Mode
108    AltOpenDrain = 3,
109}
110impl From<CONFIG> for u8 {
111    #[inline(always)]
112    fn from(variant: CONFIG) -> Self {
113        variant as _
114    }
115}
116impl crate::FieldSpec for CONFIG {
117    type Ux = u8;
118}
119impl crate::IsEnum for CONFIG {}
120///Field `CNF(0-7)` reader - Port n.%s configuration bits
121pub type CNF_R = crate::FieldReader<CONFIG>;
122impl CNF_R {
123    ///Get enumerated values variant
124    #[inline(always)]
125    pub const fn variant(&self) -> CONFIG {
126        match self.bits {
127            0 => CONFIG::PushPull,
128            1 => CONFIG::OpenDrain,
129            2 => CONFIG::AltPushPull,
130            3 => CONFIG::AltOpenDrain,
131            _ => unreachable!(),
132        }
133    }
134    ///Analog mode / Push-Pull mode
135    #[inline(always)]
136    pub fn is_push_pull(&self) -> bool {
137        *self == CONFIG::PushPull
138    }
139    ///Floating input (reset state) / Open Drain-Mode
140    #[inline(always)]
141    pub fn is_open_drain(&self) -> bool {
142        *self == CONFIG::OpenDrain
143    }
144    ///Input with pull-up/pull-down / Alternate Function Push-Pull Mode
145    #[inline(always)]
146    pub fn is_alt_push_pull(&self) -> bool {
147        *self == CONFIG::AltPushPull
148    }
149    ///Alternate Function Open-Drain Mode
150    #[inline(always)]
151    pub fn is_alt_open_drain(&self) -> bool {
152        *self == CONFIG::AltOpenDrain
153    }
154}
155///Field `CNF(0-7)` writer - Port n.%s configuration bits
156pub type CNF_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CONFIG, crate::Safe>;
157impl<'a, REG> CNF_W<'a, REG>
158where
159    REG: crate::Writable + crate::RegisterSpec,
160    REG::Ux: From<u8>,
161{
162    ///Analog mode / Push-Pull mode
163    #[inline(always)]
164    pub fn push_pull(self) -> &'a mut crate::W<REG> {
165        self.variant(CONFIG::PushPull)
166    }
167    ///Floating input (reset state) / Open Drain-Mode
168    #[inline(always)]
169    pub fn open_drain(self) -> &'a mut crate::W<REG> {
170        self.variant(CONFIG::OpenDrain)
171    }
172    ///Input with pull-up/pull-down / Alternate Function Push-Pull Mode
173    #[inline(always)]
174    pub fn alt_push_pull(self) -> &'a mut crate::W<REG> {
175        self.variant(CONFIG::AltPushPull)
176    }
177    ///Alternate Function Open-Drain Mode
178    #[inline(always)]
179    pub fn alt_open_drain(self) -> &'a mut crate::W<REG> {
180        self.variant(CONFIG::AltOpenDrain)
181    }
182}
183impl R {
184    ///Port n.(0-7) mode bits
185    ///
186    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MODE0` field.</div>
187    #[inline(always)]
188    pub fn mode(&self, n: u8) -> MODE_R {
189        #[allow(clippy::no_effect)] [(); 8][n as usize];
190        MODE_R::new(((self.bits >> (n * 4)) & 3) as u8)
191    }
192    ///Iterator for array of:
193    ///Port n.(0-7) mode bits
194    #[inline(always)]
195    pub fn mode_iter(&self) -> impl Iterator<Item = MODE_R> + '_ {
196        (0..8).map(move |n| MODE_R::new(((self.bits >> (n * 4)) & 3) as u8))
197    }
198    ///Bits 0:1 - Port n.0 mode bits
199    #[inline(always)]
200    pub fn mode0(&self) -> MODE_R {
201        MODE_R::new((self.bits & 3) as u8)
202    }
203    ///Bits 4:5 - Port n.1 mode bits
204    #[inline(always)]
205    pub fn mode1(&self) -> MODE_R {
206        MODE_R::new(((self.bits >> 4) & 3) as u8)
207    }
208    ///Bits 8:9 - Port n.2 mode bits
209    #[inline(always)]
210    pub fn mode2(&self) -> MODE_R {
211        MODE_R::new(((self.bits >> 8) & 3) as u8)
212    }
213    ///Bits 12:13 - Port n.3 mode bits
214    #[inline(always)]
215    pub fn mode3(&self) -> MODE_R {
216        MODE_R::new(((self.bits >> 12) & 3) as u8)
217    }
218    ///Bits 16:17 - Port n.4 mode bits
219    #[inline(always)]
220    pub fn mode4(&self) -> MODE_R {
221        MODE_R::new(((self.bits >> 16) & 3) as u8)
222    }
223    ///Bits 20:21 - Port n.5 mode bits
224    #[inline(always)]
225    pub fn mode5(&self) -> MODE_R {
226        MODE_R::new(((self.bits >> 20) & 3) as u8)
227    }
228    ///Bits 24:25 - Port n.6 mode bits
229    #[inline(always)]
230    pub fn mode6(&self) -> MODE_R {
231        MODE_R::new(((self.bits >> 24) & 3) as u8)
232    }
233    ///Bits 28:29 - Port n.7 mode bits
234    #[inline(always)]
235    pub fn mode7(&self) -> MODE_R {
236        MODE_R::new(((self.bits >> 28) & 3) as u8)
237    }
238    ///Port n.(0-7) configuration bits
239    ///
240    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CNF0` field.</div>
241    #[inline(always)]
242    pub fn cnf(&self, n: u8) -> CNF_R {
243        #[allow(clippy::no_effect)] [(); 8][n as usize];
244        CNF_R::new(((self.bits >> (n * 4 + 2)) & 3) as u8)
245    }
246    ///Iterator for array of:
247    ///Port n.(0-7) configuration bits
248    #[inline(always)]
249    pub fn cnf_iter(&self) -> impl Iterator<Item = CNF_R> + '_ {
250        (0..8).map(move |n| CNF_R::new(((self.bits >> (n * 4 + 2)) & 3) as u8))
251    }
252    ///Bits 2:3 - Port n.0 configuration bits
253    #[inline(always)]
254    pub fn cnf0(&self) -> CNF_R {
255        CNF_R::new(((self.bits >> 2) & 3) as u8)
256    }
257    ///Bits 6:7 - Port n.1 configuration bits
258    #[inline(always)]
259    pub fn cnf1(&self) -> CNF_R {
260        CNF_R::new(((self.bits >> 6) & 3) as u8)
261    }
262    ///Bits 10:11 - Port n.2 configuration bits
263    #[inline(always)]
264    pub fn cnf2(&self) -> CNF_R {
265        CNF_R::new(((self.bits >> 10) & 3) as u8)
266    }
267    ///Bits 14:15 - Port n.3 configuration bits
268    #[inline(always)]
269    pub fn cnf3(&self) -> CNF_R {
270        CNF_R::new(((self.bits >> 14) & 3) as u8)
271    }
272    ///Bits 18:19 - Port n.4 configuration bits
273    #[inline(always)]
274    pub fn cnf4(&self) -> CNF_R {
275        CNF_R::new(((self.bits >> 18) & 3) as u8)
276    }
277    ///Bits 22:23 - Port n.5 configuration bits
278    #[inline(always)]
279    pub fn cnf5(&self) -> CNF_R {
280        CNF_R::new(((self.bits >> 22) & 3) as u8)
281    }
282    ///Bits 26:27 - Port n.6 configuration bits
283    #[inline(always)]
284    pub fn cnf6(&self) -> CNF_R {
285        CNF_R::new(((self.bits >> 26) & 3) as u8)
286    }
287    ///Bits 30:31 - Port n.7 configuration bits
288    #[inline(always)]
289    pub fn cnf7(&self) -> CNF_R {
290        CNF_R::new(((self.bits >> 30) & 3) as u8)
291    }
292}
293impl core::fmt::Debug for R {
294    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
295        f.debug_struct("CRL")
296            .field("mode0", &self.mode0())
297            .field("mode1", &self.mode1())
298            .field("mode2", &self.mode2())
299            .field("mode3", &self.mode3())
300            .field("mode4", &self.mode4())
301            .field("mode5", &self.mode5())
302            .field("mode6", &self.mode6())
303            .field("mode7", &self.mode7())
304            .field("cnf0", &self.cnf0())
305            .field("cnf1", &self.cnf1())
306            .field("cnf2", &self.cnf2())
307            .field("cnf3", &self.cnf3())
308            .field("cnf4", &self.cnf4())
309            .field("cnf5", &self.cnf5())
310            .field("cnf6", &self.cnf6())
311            .field("cnf7", &self.cnf7())
312            .finish()
313    }
314}
315impl W {
316    ///Port n.(0-7) mode bits
317    ///
318    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MODE0` field.</div>
319    #[inline(always)]
320    pub fn mode(&mut self, n: u8) -> MODE_W<CRLrs> {
321        #[allow(clippy::no_effect)] [(); 8][n as usize];
322        MODE_W::new(self, n * 4)
323    }
324    ///Bits 0:1 - Port n.0 mode bits
325    #[inline(always)]
326    pub fn mode0(&mut self) -> MODE_W<CRLrs> {
327        MODE_W::new(self, 0)
328    }
329    ///Bits 4:5 - Port n.1 mode bits
330    #[inline(always)]
331    pub fn mode1(&mut self) -> MODE_W<CRLrs> {
332        MODE_W::new(self, 4)
333    }
334    ///Bits 8:9 - Port n.2 mode bits
335    #[inline(always)]
336    pub fn mode2(&mut self) -> MODE_W<CRLrs> {
337        MODE_W::new(self, 8)
338    }
339    ///Bits 12:13 - Port n.3 mode bits
340    #[inline(always)]
341    pub fn mode3(&mut self) -> MODE_W<CRLrs> {
342        MODE_W::new(self, 12)
343    }
344    ///Bits 16:17 - Port n.4 mode bits
345    #[inline(always)]
346    pub fn mode4(&mut self) -> MODE_W<CRLrs> {
347        MODE_W::new(self, 16)
348    }
349    ///Bits 20:21 - Port n.5 mode bits
350    #[inline(always)]
351    pub fn mode5(&mut self) -> MODE_W<CRLrs> {
352        MODE_W::new(self, 20)
353    }
354    ///Bits 24:25 - Port n.6 mode bits
355    #[inline(always)]
356    pub fn mode6(&mut self) -> MODE_W<CRLrs> {
357        MODE_W::new(self, 24)
358    }
359    ///Bits 28:29 - Port n.7 mode bits
360    #[inline(always)]
361    pub fn mode7(&mut self) -> MODE_W<CRLrs> {
362        MODE_W::new(self, 28)
363    }
364    ///Port n.(0-7) configuration bits
365    ///
366    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CNF0` field.</div>
367    #[inline(always)]
368    pub fn cnf(&mut self, n: u8) -> CNF_W<CRLrs> {
369        #[allow(clippy::no_effect)] [(); 8][n as usize];
370        CNF_W::new(self, n * 4 + 2)
371    }
372    ///Bits 2:3 - Port n.0 configuration bits
373    #[inline(always)]
374    pub fn cnf0(&mut self) -> CNF_W<CRLrs> {
375        CNF_W::new(self, 2)
376    }
377    ///Bits 6:7 - Port n.1 configuration bits
378    #[inline(always)]
379    pub fn cnf1(&mut self) -> CNF_W<CRLrs> {
380        CNF_W::new(self, 6)
381    }
382    ///Bits 10:11 - Port n.2 configuration bits
383    #[inline(always)]
384    pub fn cnf2(&mut self) -> CNF_W<CRLrs> {
385        CNF_W::new(self, 10)
386    }
387    ///Bits 14:15 - Port n.3 configuration bits
388    #[inline(always)]
389    pub fn cnf3(&mut self) -> CNF_W<CRLrs> {
390        CNF_W::new(self, 14)
391    }
392    ///Bits 18:19 - Port n.4 configuration bits
393    #[inline(always)]
394    pub fn cnf4(&mut self) -> CNF_W<CRLrs> {
395        CNF_W::new(self, 18)
396    }
397    ///Bits 22:23 - Port n.5 configuration bits
398    #[inline(always)]
399    pub fn cnf5(&mut self) -> CNF_W<CRLrs> {
400        CNF_W::new(self, 22)
401    }
402    ///Bits 26:27 - Port n.6 configuration bits
403    #[inline(always)]
404    pub fn cnf6(&mut self) -> CNF_W<CRLrs> {
405        CNF_W::new(self, 26)
406    }
407    ///Bits 30:31 - Port n.7 configuration bits
408    #[inline(always)]
409    pub fn cnf7(&mut self) -> CNF_W<CRLrs> {
410        CNF_W::new(self, 30)
411    }
412}
413/**Port configuration register low (GPIOn_CRL)
414
415You can [`read`](crate::Reg::read) this register and get [`crl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
416
417See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#GPIOA:CRL)*/
418pub struct CRLrs;
419impl crate::RegisterSpec for CRLrs {
420    type Ux = u32;
421}
422///`read()` method returns [`crl::R`](R) reader structure
423impl crate::Readable for CRLrs {}
424///`write(|w| ..)` method takes [`crl::W`](W) writer structure
425impl crate::Writable for CRLrs {
426    type Safety = crate::Unsafe;
427}
428///`reset()` method sets CRL to value 0x4444_4444
429impl crate::Resettable for CRLrs {
430    const RESET_VALUE: u32 = 0x4444_4444;
431}
stm32f1_staging/stm32f103/gpioa/crl.rs

stm32f1_staging/stm32f103/gpioa/
crl.rs
