stm32f1_staging/stm32f100/
tim12.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved7: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    _reserved11: [u8; 0x04],
18    ccr: [CCR; 2],
19}
20impl RegisterBlock {
21    ///0x00 - control register 1
22    #[inline(always)]
23    pub const fn cr1(&self) -> &CR1 {
24        &self.cr1
25    }
26    ///0x04 - control register 2
27    #[inline(always)]
28    pub const fn cr2(&self) -> &CR2 {
29        &self.cr2
30    }
31    ///0x08 - slave mode control register
32    #[inline(always)]
33    pub const fn smcr(&self) -> &SMCR {
34        &self.smcr
35    }
36    ///0x0c - DMA/Interrupt enable register
37    #[inline(always)]
38    pub const fn dier(&self) -> &DIER {
39        &self.dier
40    }
41    ///0x10 - status register
42    #[inline(always)]
43    pub const fn sr(&self) -> &SR {
44        &self.sr
45    }
46    ///0x14 - event generation register
47    #[inline(always)]
48    pub const fn egr(&self) -> &EGR {
49        &self.egr
50    }
51    ///0x18 - capture/compare mode register 1 (input mode)
52    #[inline(always)]
53    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
54        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
55    }
56    ///0x18 - capture/compare mode register 1 (output mode)
57    #[inline(always)]
58    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
59        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
60    }
61    ///0x20 - capture/compare enable register
62    #[inline(always)]
63    pub const fn ccer(&self) -> &CCER {
64        &self.ccer
65    }
66    ///0x24 - counter
67    #[inline(always)]
68    pub const fn cnt(&self) -> &CNT {
69        &self.cnt
70    }
71    ///0x28 - prescaler
72    #[inline(always)]
73    pub const fn psc(&self) -> &PSC {
74        &self.psc
75    }
76    ///0x2c - auto-reload register
77    #[inline(always)]
78    pub const fn arr(&self) -> &ARR {
79        &self.arr
80    }
81    ///0x34..0x3c - capture/compare register
82    ///
83    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
84    #[inline(always)]
85    pub const fn ccr(&self, n: usize) -> &CCR {
86        &self.ccr[n]
87    }
88    ///Iterator for array of:
89    ///0x34..0x3c - capture/compare register
90    #[inline(always)]
91    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
92        self.ccr.iter()
93    }
94    ///0x34 - capture/compare register
95    #[inline(always)]
96    pub const fn ccr1(&self) -> &CCR {
97        self.ccr(0)
98    }
99    ///0x38 - capture/compare register
100    #[inline(always)]
101    pub const fn ccr2(&self) -> &CCR {
102        self.ccr(1)
103    }
104}
105/**CR1 (rw) register accessor: control register 1
106
107You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
108
109See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:CR1)
110
111For information about available fields see [`mod@cr1`] module*/
112pub type CR1 = crate::Reg<cr1::CR1rs>;
113///control register 1
114pub mod cr1;
115/**CR2 (rw) register accessor: control register 2
116
117You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
118
119See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:CR2)
120
121For information about available fields see [`mod@cr2`] module*/
122pub type CR2 = crate::Reg<cr2::CR2rs>;
123///control register 2
124pub mod cr2;
125/**SMCR (rw) register accessor: slave mode control register
126
127You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
128
129See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:SMCR)
130
131For information about available fields see [`mod@smcr`] module*/
132pub type SMCR = crate::Reg<smcr::SMCRrs>;
133///slave mode control register
134pub mod smcr;
135/**DIER (rw) register accessor: DMA/Interrupt enable register
136
137You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
138
139See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:DIER)
140
141For information about available fields see [`mod@dier`] module*/
142pub type DIER = crate::Reg<dier::DIERrs>;
143///DMA/Interrupt enable register
144pub mod dier;
145/**SR (rw) register accessor: status register
146
147You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
148
149See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:SR)
150
151For information about available fields see [`mod@sr`] module*/
152pub type SR = crate::Reg<sr::SRrs>;
153///status register
154pub mod sr;
155/**EGR (w) register accessor: event generation register
156
157You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
158
159See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:EGR)
160
161For information about available fields see [`mod@egr`] module*/
162pub type EGR = crate::Reg<egr::EGRrs>;
163///event generation register
164pub mod egr;
165/**CCMR1_Output (rw) register accessor: capture/compare mode register 1 (output mode)
166
167You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
168
169See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:CCMR1_Output)
170
171For information about available fields see [`mod@ccmr1_output`] module*/
172#[doc(alias = "CCMR1_Output")]
173pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
174///capture/compare mode register 1 (output mode)
175pub mod ccmr1_output;
176/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
177
178You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
179
180See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:CCMR1_Input)
181
182For information about available fields see [`mod@ccmr1_input`] module*/
183#[doc(alias = "CCMR1_Input")]
184pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
185///capture/compare mode register 1 (input mode)
186pub mod ccmr1_input;
187/**CCER (rw) register accessor: capture/compare enable register
188
189You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
190
191See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:CCER)
192
193For information about available fields see [`mod@ccer`] module*/
194pub type CCER = crate::Reg<ccer::CCERrs>;
195///capture/compare enable register
196pub mod ccer;
197/**CNT (rw) register accessor: counter
198
199You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
200
201See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:CNT)
202
203For information about available fields see [`mod@cnt`] module*/
204pub type CNT = crate::Reg<cnt::CNTrs>;
205///counter
206pub mod cnt;
207/**PSC (rw) register accessor: prescaler
208
209You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
210
211See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:PSC)
212
213For information about available fields see [`mod@psc`] module*/
214pub type PSC = crate::Reg<psc::PSCrs>;
215///prescaler
216pub mod psc;
217/**ARR (rw) register accessor: auto-reload register
218
219You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
220
221See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:ARR)
222
223For information about available fields see [`mod@arr`] module*/
224pub type ARR = crate::Reg<arr::ARRrs>;
225///auto-reload register
226pub mod arr;
227/**CCR (rw) register accessor: capture/compare register
228
229You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
230
231See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:CCR[1])
232
233For information about available fields see [`mod@ccr`] module*/
234pub type CCR = crate::Reg<ccr::CCRrs>;
235///capture/compare register
236pub mod ccr;
stm32f1_staging/stm32f100/tim12.rs

stm32f1_staging/stm32f100/
tim12.rs
