stm32f1_staging/stm32f100/tim1/
ccer.rs

1///Register `CCER` reader
2pub type R = crate::R<CCERrs>;
3///Register `CCER` writer
4pub type W = crate::W<CCERrs>;
5/**Capture/Compare %s output enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CC1E {
11    ///0: Capture disabled
12    Disabled = 0,
13    ///1: Capture enabled
14    Enabled = 1,
15}
16impl From<CC1E> for bool {
17    #[inline(always)]
18    fn from(variant: CC1E) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCE(1-4)` reader - Capture/Compare %s output enable
23pub type CCE_R = crate::BitReader<CC1E>;
24impl CCE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CC1E {
28        match self.bits {
29            false => CC1E::Disabled,
30            true => CC1E::Enabled,
31        }
32    }
33    ///Capture disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == CC1E::Disabled
37    }
38    ///Capture enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == CC1E::Enabled
42    }
43}
44///Field `CCE(1-4)` writer - Capture/Compare %s output enable
45pub type CCE_W<'a, REG> = crate::BitWriter<'a, REG, CC1E>;
46impl<'a, REG> CCE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Capture disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(CC1E::Disabled)
54    }
55    ///Capture enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(CC1E::Enabled)
59    }
60}
61/**Capture/Compare %s output Polarity
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CC1P {
67    ///0: Noninverted/rising edge
68    RisingEdge = 0,
69    ///1: Inverted/falling edge
70    FallingEdge = 1,
71}
72impl From<CC1P> for bool {
73    #[inline(always)]
74    fn from(variant: CC1P) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCP(1-4)` reader - Capture/Compare %s output Polarity
79pub type CCP_R = crate::BitReader<CC1P>;
80impl CCP_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CC1P {
84        match self.bits {
85            false => CC1P::RisingEdge,
86            true => CC1P::FallingEdge,
87        }
88    }
89    ///Noninverted/rising edge
90    #[inline(always)]
91    pub fn is_rising_edge(&self) -> bool {
92        *self == CC1P::RisingEdge
93    }
94    ///Inverted/falling edge
95    #[inline(always)]
96    pub fn is_falling_edge(&self) -> bool {
97        *self == CC1P::FallingEdge
98    }
99}
100///Field `CCP(1-4)` writer - Capture/Compare %s output Polarity
101pub type CCP_W<'a, REG> = crate::BitWriter<'a, REG, CC1P>;
102impl<'a, REG> CCP_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Noninverted/rising edge
107    #[inline(always)]
108    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
109        self.variant(CC1P::RisingEdge)
110    }
111    ///Inverted/falling edge
112    #[inline(always)]
113    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
114        self.variant(CC1P::FallingEdge)
115    }
116}
117/**Capture/Compare %s complementary output enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum CC1NE {
123    ///0: Complementary output disabled
124    Disabled = 0,
125    ///1: Complementary output enabled
126    Enabled = 1,
127}
128impl From<CC1NE> for bool {
129    #[inline(always)]
130    fn from(variant: CC1NE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `CCNE(1-3)` reader - Capture/Compare %s complementary output enable
135pub type CCNE_R = crate::BitReader<CC1NE>;
136impl CCNE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> CC1NE {
140        match self.bits {
141            false => CC1NE::Disabled,
142            true => CC1NE::Enabled,
143        }
144    }
145    ///Complementary output disabled
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == CC1NE::Disabled
149    }
150    ///Complementary output enabled
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == CC1NE::Enabled
154    }
155}
156///Field `CCNE(1-3)` writer - Capture/Compare %s complementary output enable
157pub type CCNE_W<'a, REG> = crate::BitWriter<'a, REG, CC1NE>;
158impl<'a, REG> CCNE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Complementary output disabled
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(CC1NE::Disabled)
166    }
167    ///Complementary output enabled
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(CC1NE::Enabled)
171    }
172}
173/**Capture/Compare %s output Polarity
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum CC1NP {
179    ///0: OCxN active high
180    ActiveHigh = 0,
181    ///1: OCxN active low
182    ActiveLow = 1,
183}
184impl From<CC1NP> for bool {
185    #[inline(always)]
186    fn from(variant: CC1NP) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `CCNP(1-3)` reader - Capture/Compare %s output Polarity
191pub type CCNP_R = crate::BitReader<CC1NP>;
192impl CCNP_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> CC1NP {
196        match self.bits {
197            false => CC1NP::ActiveHigh,
198            true => CC1NP::ActiveLow,
199        }
200    }
201    ///OCxN active high
202    #[inline(always)]
203    pub fn is_active_high(&self) -> bool {
204        *self == CC1NP::ActiveHigh
205    }
206    ///OCxN active low
207    #[inline(always)]
208    pub fn is_active_low(&self) -> bool {
209        *self == CC1NP::ActiveLow
210    }
211}
212///Field `CCNP(1-3)` writer - Capture/Compare %s output Polarity
213pub type CCNP_W<'a, REG> = crate::BitWriter<'a, REG, CC1NP>;
214impl<'a, REG> CCNP_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///OCxN active high
219    #[inline(always)]
220    pub fn active_high(self) -> &'a mut crate::W<REG> {
221        self.variant(CC1NP::ActiveHigh)
222    }
223    ///OCxN active low
224    #[inline(always)]
225    pub fn active_low(self) -> &'a mut crate::W<REG> {
226        self.variant(CC1NP::ActiveLow)
227    }
228}
229impl R {
230    ///Capture/Compare (1-4) output enable
231    ///
232    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
233    #[inline(always)]
234    pub fn cce(&self, n: u8) -> CCE_R {
235        #[allow(clippy::no_effect)] [(); 4][n as usize];
236        CCE_R::new(((self.bits >> (n * 4)) & 1) != 0)
237    }
238    ///Iterator for array of:
239    ///Capture/Compare (1-4) output enable
240    #[inline(always)]
241    pub fn cce_iter(&self) -> impl Iterator<Item = CCE_R> + '_ {
242        (0..4).map(move |n| CCE_R::new(((self.bits >> (n * 4)) & 1) != 0))
243    }
244    ///Bit 0 - Capture/Compare 1 output enable
245    #[inline(always)]
246    pub fn cc1e(&self) -> CCE_R {
247        CCE_R::new((self.bits & 1) != 0)
248    }
249    ///Bit 4 - Capture/Compare 2 output enable
250    #[inline(always)]
251    pub fn cc2e(&self) -> CCE_R {
252        CCE_R::new(((self.bits >> 4) & 1) != 0)
253    }
254    ///Bit 8 - Capture/Compare 3 output enable
255    #[inline(always)]
256    pub fn cc3e(&self) -> CCE_R {
257        CCE_R::new(((self.bits >> 8) & 1) != 0)
258    }
259    ///Bit 12 - Capture/Compare 4 output enable
260    #[inline(always)]
261    pub fn cc4e(&self) -> CCE_R {
262        CCE_R::new(((self.bits >> 12) & 1) != 0)
263    }
264    ///Capture/Compare (1-4) output Polarity
265    ///
266    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
267    #[inline(always)]
268    pub fn ccp(&self, n: u8) -> CCP_R {
269        #[allow(clippy::no_effect)] [(); 4][n as usize];
270        CCP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0)
271    }
272    ///Iterator for array of:
273    ///Capture/Compare (1-4) output Polarity
274    #[inline(always)]
275    pub fn ccp_iter(&self) -> impl Iterator<Item = CCP_R> + '_ {
276        (0..4).map(move |n| CCP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0))
277    }
278    ///Bit 1 - Capture/Compare 1 output Polarity
279    #[inline(always)]
280    pub fn cc1p(&self) -> CCP_R {
281        CCP_R::new(((self.bits >> 1) & 1) != 0)
282    }
283    ///Bit 5 - Capture/Compare 2 output Polarity
284    #[inline(always)]
285    pub fn cc2p(&self) -> CCP_R {
286        CCP_R::new(((self.bits >> 5) & 1) != 0)
287    }
288    ///Bit 9 - Capture/Compare 3 output Polarity
289    #[inline(always)]
290    pub fn cc3p(&self) -> CCP_R {
291        CCP_R::new(((self.bits >> 9) & 1) != 0)
292    }
293    ///Bit 13 - Capture/Compare 4 output Polarity
294    #[inline(always)]
295    pub fn cc4p(&self) -> CCP_R {
296        CCP_R::new(((self.bits >> 13) & 1) != 0)
297    }
298    ///Capture/Compare (1-3) complementary output enable
299    ///
300    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NE` field.</div>
301    #[inline(always)]
302    pub fn ccne(&self, n: u8) -> CCNE_R {
303        #[allow(clippy::no_effect)] [(); 3][n as usize];
304        CCNE_R::new(((self.bits >> (n * 4 + 2)) & 1) != 0)
305    }
306    ///Iterator for array of:
307    ///Capture/Compare (1-3) complementary output enable
308    #[inline(always)]
309    pub fn ccne_iter(&self) -> impl Iterator<Item = CCNE_R> + '_ {
310        (0..3).map(move |n| CCNE_R::new(((self.bits >> (n * 4 + 2)) & 1) != 0))
311    }
312    ///Bit 2 - Capture/Compare 1 complementary output enable
313    #[inline(always)]
314    pub fn cc1ne(&self) -> CCNE_R {
315        CCNE_R::new(((self.bits >> 2) & 1) != 0)
316    }
317    ///Bit 6 - Capture/Compare 2 complementary output enable
318    #[inline(always)]
319    pub fn cc2ne(&self) -> CCNE_R {
320        CCNE_R::new(((self.bits >> 6) & 1) != 0)
321    }
322    ///Bit 10 - Capture/Compare 3 complementary output enable
323    #[inline(always)]
324    pub fn cc3ne(&self) -> CCNE_R {
325        CCNE_R::new(((self.bits >> 10) & 1) != 0)
326    }
327    ///Capture/Compare (1-3) output Polarity
328    ///
329    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
330    #[inline(always)]
331    pub fn ccnp(&self, n: u8) -> CCNP_R {
332        #[allow(clippy::no_effect)] [(); 3][n as usize];
333        CCNP_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0)
334    }
335    ///Iterator for array of:
336    ///Capture/Compare (1-3) output Polarity
337    #[inline(always)]
338    pub fn ccnp_iter(&self) -> impl Iterator<Item = CCNP_R> + '_ {
339        (0..3).map(move |n| CCNP_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0))
340    }
341    ///Bit 3 - Capture/Compare 1 output Polarity
342    #[inline(always)]
343    pub fn cc1np(&self) -> CCNP_R {
344        CCNP_R::new(((self.bits >> 3) & 1) != 0)
345    }
346    ///Bit 7 - Capture/Compare 2 output Polarity
347    #[inline(always)]
348    pub fn cc2np(&self) -> CCNP_R {
349        CCNP_R::new(((self.bits >> 7) & 1) != 0)
350    }
351    ///Bit 11 - Capture/Compare 3 output Polarity
352    #[inline(always)]
353    pub fn cc3np(&self) -> CCNP_R {
354        CCNP_R::new(((self.bits >> 11) & 1) != 0)
355    }
356}
357impl core::fmt::Debug for R {
358    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
359        f.debug_struct("CCER")
360            .field("cc1p", &self.cc1p())
361            .field("cc2p", &self.cc2p())
362            .field("cc3p", &self.cc3p())
363            .field("cc4p", &self.cc4p())
364            .field("cc1e", &self.cc1e())
365            .field("cc2e", &self.cc2e())
366            .field("cc3e", &self.cc3e())
367            .field("cc4e", &self.cc4e())
368            .field("cc1np", &self.cc1np())
369            .field("cc2np", &self.cc2np())
370            .field("cc3np", &self.cc3np())
371            .field("cc1ne", &self.cc1ne())
372            .field("cc2ne", &self.cc2ne())
373            .field("cc3ne", &self.cc3ne())
374            .finish()
375    }
376}
377impl W {
378    ///Capture/Compare (1-4) output enable
379    ///
380    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
381    #[inline(always)]
382    pub fn cce(&mut self, n: u8) -> CCE_W<CCERrs> {
383        #[allow(clippy::no_effect)] [(); 4][n as usize];
384        CCE_W::new(self, n * 4)
385    }
386    ///Bit 0 - Capture/Compare 1 output enable
387    #[inline(always)]
388    pub fn cc1e(&mut self) -> CCE_W<CCERrs> {
389        CCE_W::new(self, 0)
390    }
391    ///Bit 4 - Capture/Compare 2 output enable
392    #[inline(always)]
393    pub fn cc2e(&mut self) -> CCE_W<CCERrs> {
394        CCE_W::new(self, 4)
395    }
396    ///Bit 8 - Capture/Compare 3 output enable
397    #[inline(always)]
398    pub fn cc3e(&mut self) -> CCE_W<CCERrs> {
399        CCE_W::new(self, 8)
400    }
401    ///Bit 12 - Capture/Compare 4 output enable
402    #[inline(always)]
403    pub fn cc4e(&mut self) -> CCE_W<CCERrs> {
404        CCE_W::new(self, 12)
405    }
406    ///Capture/Compare (1-4) output Polarity
407    ///
408    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
409    #[inline(always)]
410    pub fn ccp(&mut self, n: u8) -> CCP_W<CCERrs> {
411        #[allow(clippy::no_effect)] [(); 4][n as usize];
412        CCP_W::new(self, n * 4 + 1)
413    }
414    ///Bit 1 - Capture/Compare 1 output Polarity
415    #[inline(always)]
416    pub fn cc1p(&mut self) -> CCP_W<CCERrs> {
417        CCP_W::new(self, 1)
418    }
419    ///Bit 5 - Capture/Compare 2 output Polarity
420    #[inline(always)]
421    pub fn cc2p(&mut self) -> CCP_W<CCERrs> {
422        CCP_W::new(self, 5)
423    }
424    ///Bit 9 - Capture/Compare 3 output Polarity
425    #[inline(always)]
426    pub fn cc3p(&mut self) -> CCP_W<CCERrs> {
427        CCP_W::new(self, 9)
428    }
429    ///Bit 13 - Capture/Compare 4 output Polarity
430    #[inline(always)]
431    pub fn cc4p(&mut self) -> CCP_W<CCERrs> {
432        CCP_W::new(self, 13)
433    }
434    ///Capture/Compare (1-3) complementary output enable
435    ///
436    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NE` field.</div>
437    #[inline(always)]
438    pub fn ccne(&mut self, n: u8) -> CCNE_W<CCERrs> {
439        #[allow(clippy::no_effect)] [(); 3][n as usize];
440        CCNE_W::new(self, n * 4 + 2)
441    }
442    ///Bit 2 - Capture/Compare 1 complementary output enable
443    #[inline(always)]
444    pub fn cc1ne(&mut self) -> CCNE_W<CCERrs> {
445        CCNE_W::new(self, 2)
446    }
447    ///Bit 6 - Capture/Compare 2 complementary output enable
448    #[inline(always)]
449    pub fn cc2ne(&mut self) -> CCNE_W<CCERrs> {
450        CCNE_W::new(self, 6)
451    }
452    ///Bit 10 - Capture/Compare 3 complementary output enable
453    #[inline(always)]
454    pub fn cc3ne(&mut self) -> CCNE_W<CCERrs> {
455        CCNE_W::new(self, 10)
456    }
457    ///Capture/Compare (1-3) output Polarity
458    ///
459    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
460    #[inline(always)]
461    pub fn ccnp(&mut self, n: u8) -> CCNP_W<CCERrs> {
462        #[allow(clippy::no_effect)] [(); 3][n as usize];
463        CCNP_W::new(self, n * 4 + 3)
464    }
465    ///Bit 3 - Capture/Compare 1 output Polarity
466    #[inline(always)]
467    pub fn cc1np(&mut self) -> CCNP_W<CCERrs> {
468        CCNP_W::new(self, 3)
469    }
470    ///Bit 7 - Capture/Compare 2 output Polarity
471    #[inline(always)]
472    pub fn cc2np(&mut self) -> CCNP_W<CCERrs> {
473        CCNP_W::new(self, 7)
474    }
475    ///Bit 11 - Capture/Compare 3 output Polarity
476    #[inline(always)]
477    pub fn cc3np(&mut self) -> CCNP_W<CCERrs> {
478        CCNP_W::new(self, 11)
479    }
480}
481/**capture/compare enable register
482
483You can [`read`](crate::Reg::read) this register and get [`ccer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
484
485See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:CCER)*/
486pub struct CCERrs;
487impl crate::RegisterSpec for CCERrs {
488    type Ux = u32;
489}
490///`read()` method returns [`ccer::R`](R) reader structure
491impl crate::Readable for CCERrs {}
492///`write(|w| ..)` method takes [`ccer::W`](W) writer structure
493impl crate::Writable for CCERrs {
494    type Safety = crate::Unsafe;
495}
496///`reset()` method sets CCER to value 0
497impl crate::Resettable for CCERrs {}
stm32f1_staging/stm32f100/tim1/ccer.rs

stm32f1_staging/stm32f100/tim1/
ccer.rs
