stm32f1_staging/stm32f100/
dac.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    swtrigr: SWTRIGR,
7    dhr12r1: DHR12R1,
8    dhr12l1: DHR12L1,
9    dhr8r1: DHR8R1,
10    dhr12r2: DHR12R2,
11    dhr12l2: DHR12L2,
12    dhr8r2: DHR8R2,
13    dhr12rd: DHR12RD,
14    dhr12ld: DHR12LD,
15    dhr8rd: DHR8RD,
16    dor1: DOR1,
17    dor2: DOR2,
18    sr: SR,
19}
20impl RegisterBlock {
21    ///0x00 - Control register (DAC_CR)
22    #[inline(always)]
23    pub const fn cr(&self) -> &CR {
24        &self.cr
25    }
26    ///0x04 - DAC software trigger register (DAC_SWTRIGR)
27    #[inline(always)]
28    pub const fn swtrigr(&self) -> &SWTRIGR {
29        &self.swtrigr
30    }
31    ///0x08 - DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
32    #[inline(always)]
33    pub const fn dhr12r1(&self) -> &DHR12R1 {
34        &self.dhr12r1
35    }
36    ///0x0c - DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
37    #[inline(always)]
38    pub const fn dhr12l1(&self) -> &DHR12L1 {
39        &self.dhr12l1
40    }
41    ///0x10 - DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
42    #[inline(always)]
43    pub const fn dhr8r1(&self) -> &DHR8R1 {
44        &self.dhr8r1
45    }
46    ///0x14 - DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
47    #[inline(always)]
48    pub const fn dhr12r2(&self) -> &DHR12R2 {
49        &self.dhr12r2
50    }
51    ///0x18 - DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
52    #[inline(always)]
53    pub const fn dhr12l2(&self) -> &DHR12L2 {
54        &self.dhr12l2
55    }
56    ///0x1c - DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
57    #[inline(always)]
58    pub const fn dhr8r2(&self) -> &DHR8R2 {
59        &self.dhr8r2
60    }
61    ///0x20 - Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
62    #[inline(always)]
63    pub const fn dhr12rd(&self) -> &DHR12RD {
64        &self.dhr12rd
65    }
66    ///0x24 - DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
67    #[inline(always)]
68    pub const fn dhr12ld(&self) -> &DHR12LD {
69        &self.dhr12ld
70    }
71    ///0x28 - DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
72    #[inline(always)]
73    pub const fn dhr8rd(&self) -> &DHR8RD {
74        &self.dhr8rd
75    }
76    ///0x2c - DAC channel1 data output register (DAC_DOR1)
77    #[inline(always)]
78    pub const fn dor1(&self) -> &DOR1 {
79        &self.dor1
80    }
81    ///0x30 - DAC channel2 data output register (DAC_DOR2)
82    #[inline(always)]
83    pub const fn dor2(&self) -> &DOR2 {
84        &self.dor2
85    }
86    ///0x34 - DAC status register
87    #[inline(always)]
88    pub const fn sr(&self) -> &SR {
89        &self.sr
90    }
91}
92/**CR (rw) register accessor: Control register (DAC_CR)
93
94You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
95
96See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:CR)
97
98For information about available fields see [`mod@cr`] module*/
99pub type CR = crate::Reg<cr::CRrs>;
100///Control register (DAC_CR)
101pub mod cr;
102/**SWTRIGR (w) register accessor: DAC software trigger register (DAC_SWTRIGR)
103
104You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swtrigr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
105
106See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:SWTRIGR)
107
108For information about available fields see [`mod@swtrigr`] module*/
109pub type SWTRIGR = crate::Reg<swtrigr::SWTRIGRrs>;
110///DAC software trigger register (DAC_SWTRIGR)
111pub mod swtrigr;
112/**DHR12R1 (rw) register accessor: DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
113
114You can [`read`](crate::Reg::read) this register and get [`dhr12r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
115
116See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:DHR12R1)
117
118For information about available fields see [`mod@dhr12r1`] module*/
119pub type DHR12R1 = crate::Reg<dhr12r1::DHR12R1rs>;
120///DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
121pub mod dhr12r1;
122/**DHR12L1 (rw) register accessor: DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
123
124You can [`read`](crate::Reg::read) this register and get [`dhr12l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
125
126See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:DHR12L1)
127
128For information about available fields see [`mod@dhr12l1`] module*/
129pub type DHR12L1 = crate::Reg<dhr12l1::DHR12L1rs>;
130///DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
131pub mod dhr12l1;
132/**DHR8R1 (rw) register accessor: DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
133
134You can [`read`](crate::Reg::read) this register and get [`dhr8r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
135
136See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:DHR8R1)
137
138For information about available fields see [`mod@dhr8r1`] module*/
139pub type DHR8R1 = crate::Reg<dhr8r1::DHR8R1rs>;
140///DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
141pub mod dhr8r1;
142/**DHR12R2 (rw) register accessor: DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
143
144You can [`read`](crate::Reg::read) this register and get [`dhr12r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
145
146See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:DHR12R2)
147
148For information about available fields see [`mod@dhr12r2`] module*/
149pub type DHR12R2 = crate::Reg<dhr12r2::DHR12R2rs>;
150///DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
151pub mod dhr12r2;
152/**DHR12L2 (rw) register accessor: DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
153
154You can [`read`](crate::Reg::read) this register and get [`dhr12l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
155
156See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:DHR12L2)
157
158For information about available fields see [`mod@dhr12l2`] module*/
159pub type DHR12L2 = crate::Reg<dhr12l2::DHR12L2rs>;
160///DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
161pub mod dhr12l2;
162/**DHR8R2 (rw) register accessor: DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
163
164You can [`read`](crate::Reg::read) this register and get [`dhr8r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
165
166See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:DHR8R2)
167
168For information about available fields see [`mod@dhr8r2`] module*/
169pub type DHR8R2 = crate::Reg<dhr8r2::DHR8R2rs>;
170///DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
171pub mod dhr8r2;
172/**DHR12RD (rw) register accessor: Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
173
174You can [`read`](crate::Reg::read) this register and get [`dhr12rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
175
176See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:DHR12RD)
177
178For information about available fields see [`mod@dhr12rd`] module*/
179pub type DHR12RD = crate::Reg<dhr12rd::DHR12RDrs>;
180///Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
181pub mod dhr12rd;
182/**DHR12LD (rw) register accessor: DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
183
184You can [`read`](crate::Reg::read) this register and get [`dhr12ld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12ld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
185
186See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:DHR12LD)
187
188For information about available fields see [`mod@dhr12ld`] module*/
189pub type DHR12LD = crate::Reg<dhr12ld::DHR12LDrs>;
190///DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
191pub mod dhr12ld;
192/**DHR8RD (rw) register accessor: DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
193
194You can [`read`](crate::Reg::read) this register and get [`dhr8rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
195
196See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:DHR8RD)
197
198For information about available fields see [`mod@dhr8rd`] module*/
199pub type DHR8RD = crate::Reg<dhr8rd::DHR8RDrs>;
200///DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
201pub mod dhr8rd;
202/**DOR1 (r) register accessor: DAC channel1 data output register (DAC_DOR1)
203
204You can [`read`](crate::Reg::read) this register and get [`dor1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
205
206See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:DOR1)
207
208For information about available fields see [`mod@dor1`] module*/
209pub type DOR1 = crate::Reg<dor1::DOR1rs>;
210///DAC channel1 data output register (DAC_DOR1)
211pub mod dor1;
212/**DOR2 (r) register accessor: DAC channel2 data output register (DAC_DOR2)
213
214You can [`read`](crate::Reg::read) this register and get [`dor2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
215
216See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:DOR2)
217
218For information about available fields see [`mod@dor2`] module*/
219pub type DOR2 = crate::Reg<dor2::DOR2rs>;
220///DAC channel2 data output register (DAC_DOR2)
221pub mod dor2;
222/**SR (rw) register accessor: DAC status register
223
224You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
225
226See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:SR)
227
228For information about available fields see [`mod@sr`] module*/
229pub type SR = crate::Reg<sr::SRrs>;
230///DAC status register
231pub mod sr;
stm32f1_staging/stm32f100/dac.rs

stm32f1_staging/stm32f100/
dac.rs
