stm32f1_staging/stm32f107/tim9/
ccer.rs

1///Register `CCER` reader
2pub type R = crate::R<CCERrs>;
3///Register `CCER` writer
4pub type W = crate::W<CCERrs>;
5/**Capture/Compare %s output enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CC1E {
11    ///0: Capture disabled
12    Disabled = 0,
13    ///1: Capture enabled
14    Enabled = 1,
15}
16impl From<CC1E> for bool {
17    #[inline(always)]
18    fn from(variant: CC1E) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCE(1-2)` reader - Capture/Compare %s output enable
23pub type CCE_R = crate::BitReader<CC1E>;
24impl CCE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CC1E {
28        match self.bits {
29            false => CC1E::Disabled,
30            true => CC1E::Enabled,
31        }
32    }
33    ///Capture disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == CC1E::Disabled
37    }
38    ///Capture enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == CC1E::Enabled
42    }
43}
44///Field `CCE(1-2)` writer - Capture/Compare %s output enable
45pub type CCE_W<'a, REG> = crate::BitWriter<'a, REG, CC1E>;
46impl<'a, REG> CCE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Capture disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(CC1E::Disabled)
54    }
55    ///Capture enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(CC1E::Enabled)
59    }
60}
61/**Capture/Compare %s output Polarity
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CC1P {
67    ///0: Noninverted/rising edge
68    RisingEdge = 0,
69    ///1: Inverted/falling edge
70    FallingEdge = 1,
71}
72impl From<CC1P> for bool {
73    #[inline(always)]
74    fn from(variant: CC1P) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCP(1-2)` reader - Capture/Compare %s output Polarity
79pub type CCP_R = crate::BitReader<CC1P>;
80impl CCP_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CC1P {
84        match self.bits {
85            false => CC1P::RisingEdge,
86            true => CC1P::FallingEdge,
87        }
88    }
89    ///Noninverted/rising edge
90    #[inline(always)]
91    pub fn is_rising_edge(&self) -> bool {
92        *self == CC1P::RisingEdge
93    }
94    ///Inverted/falling edge
95    #[inline(always)]
96    pub fn is_falling_edge(&self) -> bool {
97        *self == CC1P::FallingEdge
98    }
99}
100///Field `CCP(1-2)` writer - Capture/Compare %s output Polarity
101pub type CCP_W<'a, REG> = crate::BitWriter<'a, REG, CC1P>;
102impl<'a, REG> CCP_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Noninverted/rising edge
107    #[inline(always)]
108    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
109        self.variant(CC1P::RisingEdge)
110    }
111    ///Inverted/falling edge
112    #[inline(always)]
113    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
114        self.variant(CC1P::FallingEdge)
115    }
116}
117///Field `CCNP(1-2)` reader - Capture/Compare %s output Polarity
118pub type CCNP_R = crate::BitReader;
119///Field `CCNP(1-2)` writer - Capture/Compare %s output Polarity
120pub type CCNP_W<'a, REG> = crate::BitWriter<'a, REG>;
121impl R {
122    ///Capture/Compare (1-2) output enable
123    ///
124    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
125    #[inline(always)]
126    pub fn cce(&self, n: u8) -> CCE_R {
127        #[allow(clippy::no_effect)] [(); 2][n as usize];
128        CCE_R::new(((self.bits >> (n * 4)) & 1) != 0)
129    }
130    ///Iterator for array of:
131    ///Capture/Compare (1-2) output enable
132    #[inline(always)]
133    pub fn cce_iter(&self) -> impl Iterator<Item = CCE_R> + '_ {
134        (0..2).map(move |n| CCE_R::new(((self.bits >> (n * 4)) & 1) != 0))
135    }
136    ///Bit 0 - Capture/Compare 1 output enable
137    #[inline(always)]
138    pub fn cc1e(&self) -> CCE_R {
139        CCE_R::new((self.bits & 1) != 0)
140    }
141    ///Bit 4 - Capture/Compare 2 output enable
142    #[inline(always)]
143    pub fn cc2e(&self) -> CCE_R {
144        CCE_R::new(((self.bits >> 4) & 1) != 0)
145    }
146    ///Capture/Compare (1-2) output Polarity
147    ///
148    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
149    #[inline(always)]
150    pub fn ccp(&self, n: u8) -> CCP_R {
151        #[allow(clippy::no_effect)] [(); 2][n as usize];
152        CCP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0)
153    }
154    ///Iterator for array of:
155    ///Capture/Compare (1-2) output Polarity
156    #[inline(always)]
157    pub fn ccp_iter(&self) -> impl Iterator<Item = CCP_R> + '_ {
158        (0..2).map(move |n| CCP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0))
159    }
160    ///Bit 1 - Capture/Compare 1 output Polarity
161    #[inline(always)]
162    pub fn cc1p(&self) -> CCP_R {
163        CCP_R::new(((self.bits >> 1) & 1) != 0)
164    }
165    ///Bit 5 - Capture/Compare 2 output Polarity
166    #[inline(always)]
167    pub fn cc2p(&self) -> CCP_R {
168        CCP_R::new(((self.bits >> 5) & 1) != 0)
169    }
170    ///Capture/Compare (1-2) output Polarity
171    ///
172    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
173    #[inline(always)]
174    pub fn ccnp(&self, n: u8) -> CCNP_R {
175        #[allow(clippy::no_effect)] [(); 2][n as usize];
176        CCNP_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0)
177    }
178    ///Iterator for array of:
179    ///Capture/Compare (1-2) output Polarity
180    #[inline(always)]
181    pub fn ccnp_iter(&self) -> impl Iterator<Item = CCNP_R> + '_ {
182        (0..2).map(move |n| CCNP_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0))
183    }
184    ///Bit 3 - Capture/Compare 1 output Polarity
185    #[inline(always)]
186    pub fn cc1np(&self) -> CCNP_R {
187        CCNP_R::new(((self.bits >> 3) & 1) != 0)
188    }
189    ///Bit 7 - Capture/Compare 2 output Polarity
190    #[inline(always)]
191    pub fn cc2np(&self) -> CCNP_R {
192        CCNP_R::new(((self.bits >> 7) & 1) != 0)
193    }
194}
195impl core::fmt::Debug for R {
196    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
197        f.debug_struct("CCER")
198            .field("cc1np", &self.cc1np())
199            .field("cc2np", &self.cc2np())
200            .field("cc1p", &self.cc1p())
201            .field("cc2p", &self.cc2p())
202            .field("cc1e", &self.cc1e())
203            .field("cc2e", &self.cc2e())
204            .finish()
205    }
206}
207impl W {
208    ///Capture/Compare (1-2) output enable
209    ///
210    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
211    #[inline(always)]
212    pub fn cce(&mut self, n: u8) -> CCE_W<CCERrs> {
213        #[allow(clippy::no_effect)] [(); 2][n as usize];
214        CCE_W::new(self, n * 4)
215    }
216    ///Bit 0 - Capture/Compare 1 output enable
217    #[inline(always)]
218    pub fn cc1e(&mut self) -> CCE_W<CCERrs> {
219        CCE_W::new(self, 0)
220    }
221    ///Bit 4 - Capture/Compare 2 output enable
222    #[inline(always)]
223    pub fn cc2e(&mut self) -> CCE_W<CCERrs> {
224        CCE_W::new(self, 4)
225    }
226    ///Capture/Compare (1-2) output Polarity
227    ///
228    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
229    #[inline(always)]
230    pub fn ccp(&mut self, n: u8) -> CCP_W<CCERrs> {
231        #[allow(clippy::no_effect)] [(); 2][n as usize];
232        CCP_W::new(self, n * 4 + 1)
233    }
234    ///Bit 1 - Capture/Compare 1 output Polarity
235    #[inline(always)]
236    pub fn cc1p(&mut self) -> CCP_W<CCERrs> {
237        CCP_W::new(self, 1)
238    }
239    ///Bit 5 - Capture/Compare 2 output Polarity
240    #[inline(always)]
241    pub fn cc2p(&mut self) -> CCP_W<CCERrs> {
242        CCP_W::new(self, 5)
243    }
244    ///Capture/Compare (1-2) output Polarity
245    ///
246    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
247    #[inline(always)]
248    pub fn ccnp(&mut self, n: u8) -> CCNP_W<CCERrs> {
249        #[allow(clippy::no_effect)] [(); 2][n as usize];
250        CCNP_W::new(self, n * 4 + 3)
251    }
252    ///Bit 3 - Capture/Compare 1 output Polarity
253    #[inline(always)]
254    pub fn cc1np(&mut self) -> CCNP_W<CCERrs> {
255        CCNP_W::new(self, 3)
256    }
257    ///Bit 7 - Capture/Compare 2 output Polarity
258    #[inline(always)]
259    pub fn cc2np(&mut self) -> CCNP_W<CCERrs> {
260        CCNP_W::new(self, 7)
261    }
262}
263/**capture/compare enable register
264
265You can [`read`](crate::Reg::read) this register and get [`ccer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
266
267See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM9:CCER)*/
268pub struct CCERrs;
269impl crate::RegisterSpec for CCERrs {
270    type Ux = u32;
271}
272///`read()` method returns [`ccer::R`](R) reader structure
273impl crate::Readable for CCERrs {}
274///`write(|w| ..)` method takes [`ccer::W`](W) writer structure
275impl crate::Writable for CCERrs {
276    type Safety = crate::Unsafe;
277}
278///`reset()` method sets CCER to value 0
279impl crate::Resettable for CCERrs {}
stm32f1_staging/stm32f107/tim9/ccer.rs

stm32f1_staging/stm32f107/tim9/
ccer.rs
