stm32f1_staging/stm32f107/sdio/
mask.rs

1///Register `MASK` reader
2pub type R = crate::R<MASKrs>;
3///Register `MASK` writer
4pub type W = crate::W<MASKrs>;
5///Field `CCRCFAILIE` reader - Command CRC fail interrupt enable
6pub type CCRCFAILIE_R = crate::BitReader;
7///Field `CCRCFAILIE` writer - Command CRC fail interrupt enable
8pub type CCRCFAILIE_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DCRCFAILIE` reader - Data CRC fail interrupt enable
10pub type DCRCFAILIE_R = crate::BitReader;
11///Field `DCRCFAILIE` writer - Data CRC fail interrupt enable
12pub type DCRCFAILIE_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `CTIMEOUTIE` reader - Command timeout interrupt enable
14pub type CTIMEOUTIE_R = crate::BitReader;
15///Field `CTIMEOUTIE` writer - Command timeout interrupt enable
16pub type CTIMEOUTIE_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `DTIMEOUTIE` reader - Data timeout interrupt enable
18pub type DTIMEOUTIE_R = crate::BitReader;
19///Field `DTIMEOUTIE` writer - Data timeout interrupt enable
20pub type DTIMEOUTIE_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `TXUNDERRIE` reader - Tx FIFO underrun error interrupt enable
22pub type TXUNDERRIE_R = crate::BitReader;
23///Field `TXUNDERRIE` writer - Tx FIFO underrun error interrupt enable
24pub type TXUNDERRIE_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `RXOVERRIE` reader - Rx FIFO overrun error interrupt enable
26pub type RXOVERRIE_R = crate::BitReader;
27///Field `RXOVERRIE` writer - Rx FIFO overrun error interrupt enable
28pub type RXOVERRIE_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `CMDRENDIE` reader - Command response received interrupt enable
30pub type CMDRENDIE_R = crate::BitReader;
31///Field `CMDRENDIE` writer - Command response received interrupt enable
32pub type CMDRENDIE_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `CMDSENTIE` reader - Command sent interrupt enable
34pub type CMDSENTIE_R = crate::BitReader;
35///Field `CMDSENTIE` writer - Command sent interrupt enable
36pub type CMDSENTIE_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `DATAENDIE` reader - Data end interrupt enable
38pub type DATAENDIE_R = crate::BitReader;
39///Field `DATAENDIE` writer - Data end interrupt enable
40pub type DATAENDIE_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `STBITERRIE` reader - Start bit error interrupt enable
42pub type STBITERRIE_R = crate::BitReader;
43///Field `STBITERRIE` writer - Start bit error interrupt enable
44pub type STBITERRIE_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `DBCKENDIE` reader - Data block end interrupt enable
46pub type DBCKENDIE_R = crate::BitReader;
47///Field `DBCKENDIE` writer - Data block end interrupt enable
48pub type DBCKENDIE_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `CMDACTIE` reader - Command acting interrupt enable
50pub type CMDACTIE_R = crate::BitReader;
51///Field `CMDACTIE` writer - Command acting interrupt enable
52pub type CMDACTIE_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `TXACTIE` reader - Data transmit acting interrupt enable
54pub type TXACTIE_R = crate::BitReader;
55///Field `TXACTIE` writer - Data transmit acting interrupt enable
56pub type TXACTIE_W<'a, REG> = crate::BitWriter<'a, REG>;
57///Field `RXACTIE` reader - Data receive acting interrupt enable
58pub type RXACTIE_R = crate::BitReader;
59///Field `RXACTIE` writer - Data receive acting interrupt enable
60pub type RXACTIE_W<'a, REG> = crate::BitWriter<'a, REG>;
61///Field `TXFIFOHEIE` reader - Tx FIFO half empty interrupt enable
62pub type TXFIFOHEIE_R = crate::BitReader;
63///Field `TXFIFOHEIE` writer - Tx FIFO half empty interrupt enable
64pub type TXFIFOHEIE_W<'a, REG> = crate::BitWriter<'a, REG>;
65///Field `RXFIFOHFIE` reader - Rx FIFO half full interrupt enable
66pub type RXFIFOHFIE_R = crate::BitReader;
67///Field `RXFIFOHFIE` writer - Rx FIFO half full interrupt enable
68pub type RXFIFOHFIE_W<'a, REG> = crate::BitWriter<'a, REG>;
69///Field `TXFIFOFIE` reader - Tx FIFO full interrupt enable
70pub type TXFIFOFIE_R = crate::BitReader;
71///Field `TXFIFOFIE` writer - Tx FIFO full interrupt enable
72pub type TXFIFOFIE_W<'a, REG> = crate::BitWriter<'a, REG>;
73///Field `RXFIFOFIE` reader - Rx FIFO full interrupt enable
74pub type RXFIFOFIE_R = crate::BitReader;
75///Field `RXFIFOFIE` writer - Rx FIFO full interrupt enable
76pub type RXFIFOFIE_W<'a, REG> = crate::BitWriter<'a, REG>;
77///Field `TXFIFOEIE` reader - Tx FIFO empty interrupt enable
78pub type TXFIFOEIE_R = crate::BitReader;
79///Field `TXFIFOEIE` writer - Tx FIFO empty interrupt enable
80pub type TXFIFOEIE_W<'a, REG> = crate::BitWriter<'a, REG>;
81///Field `RXFIFOEIE` reader - Rx FIFO empty interrupt enable
82pub type RXFIFOEIE_R = crate::BitReader;
83///Field `RXFIFOEIE` writer - Rx FIFO empty interrupt enable
84pub type RXFIFOEIE_W<'a, REG> = crate::BitWriter<'a, REG>;
85///Field `TXDAVLIE` reader - Data available in Tx FIFO interrupt enable
86pub type TXDAVLIE_R = crate::BitReader;
87///Field `TXDAVLIE` writer - Data available in Tx FIFO interrupt enable
88pub type TXDAVLIE_W<'a, REG> = crate::BitWriter<'a, REG>;
89///Field `RXDAVLIE` reader - Data available in Rx FIFO interrupt enable
90pub type RXDAVLIE_R = crate::BitReader;
91///Field `RXDAVLIE` writer - Data available in Rx FIFO interrupt enable
92pub type RXDAVLIE_W<'a, REG> = crate::BitWriter<'a, REG>;
93///Field `SDIOITIE` reader - SDIO mode interrupt received interrupt enable
94pub type SDIOITIE_R = crate::BitReader;
95///Field `SDIOITIE` writer - SDIO mode interrupt received interrupt enable
96pub type SDIOITIE_W<'a, REG> = crate::BitWriter<'a, REG>;
97///Field `CEATAENDIE` reader - CE-ATA command completion signal received interrupt enable
98pub type CEATAENDIE_R = crate::BitReader;
99///Field `CEATAENDIE` writer - CE-ATA command completion signal received interrupt enable
100pub type CEATAENDIE_W<'a, REG> = crate::BitWriter<'a, REG>;
101impl R {
102    ///Bit 0 - Command CRC fail interrupt enable
103    #[inline(always)]
104    pub fn ccrcfailie(&self) -> CCRCFAILIE_R {
105        CCRCFAILIE_R::new((self.bits & 1) != 0)
106    }
107    ///Bit 1 - Data CRC fail interrupt enable
108    #[inline(always)]
109    pub fn dcrcfailie(&self) -> DCRCFAILIE_R {
110        DCRCFAILIE_R::new(((self.bits >> 1) & 1) != 0)
111    }
112    ///Bit 2 - Command timeout interrupt enable
113    #[inline(always)]
114    pub fn ctimeoutie(&self) -> CTIMEOUTIE_R {
115        CTIMEOUTIE_R::new(((self.bits >> 2) & 1) != 0)
116    }
117    ///Bit 3 - Data timeout interrupt enable
118    #[inline(always)]
119    pub fn dtimeoutie(&self) -> DTIMEOUTIE_R {
120        DTIMEOUTIE_R::new(((self.bits >> 3) & 1) != 0)
121    }
122    ///Bit 4 - Tx FIFO underrun error interrupt enable
123    #[inline(always)]
124    pub fn txunderrie(&self) -> TXUNDERRIE_R {
125        TXUNDERRIE_R::new(((self.bits >> 4) & 1) != 0)
126    }
127    ///Bit 5 - Rx FIFO overrun error interrupt enable
128    #[inline(always)]
129    pub fn rxoverrie(&self) -> RXOVERRIE_R {
130        RXOVERRIE_R::new(((self.bits >> 5) & 1) != 0)
131    }
132    ///Bit 6 - Command response received interrupt enable
133    #[inline(always)]
134    pub fn cmdrendie(&self) -> CMDRENDIE_R {
135        CMDRENDIE_R::new(((self.bits >> 6) & 1) != 0)
136    }
137    ///Bit 7 - Command sent interrupt enable
138    #[inline(always)]
139    pub fn cmdsentie(&self) -> CMDSENTIE_R {
140        CMDSENTIE_R::new(((self.bits >> 7) & 1) != 0)
141    }
142    ///Bit 8 - Data end interrupt enable
143    #[inline(always)]
144    pub fn dataendie(&self) -> DATAENDIE_R {
145        DATAENDIE_R::new(((self.bits >> 8) & 1) != 0)
146    }
147    ///Bit 9 - Start bit error interrupt enable
148    #[inline(always)]
149    pub fn stbiterrie(&self) -> STBITERRIE_R {
150        STBITERRIE_R::new(((self.bits >> 9) & 1) != 0)
151    }
152    ///Bit 10 - Data block end interrupt enable
153    #[inline(always)]
154    pub fn dbckendie(&self) -> DBCKENDIE_R {
155        DBCKENDIE_R::new(((self.bits >> 10) & 1) != 0)
156    }
157    ///Bit 11 - Command acting interrupt enable
158    #[inline(always)]
159    pub fn cmdactie(&self) -> CMDACTIE_R {
160        CMDACTIE_R::new(((self.bits >> 11) & 1) != 0)
161    }
162    ///Bit 12 - Data transmit acting interrupt enable
163    #[inline(always)]
164    pub fn txactie(&self) -> TXACTIE_R {
165        TXACTIE_R::new(((self.bits >> 12) & 1) != 0)
166    }
167    ///Bit 13 - Data receive acting interrupt enable
168    #[inline(always)]
169    pub fn rxactie(&self) -> RXACTIE_R {
170        RXACTIE_R::new(((self.bits >> 13) & 1) != 0)
171    }
172    ///Bit 14 - Tx FIFO half empty interrupt enable
173    #[inline(always)]
174    pub fn txfifoheie(&self) -> TXFIFOHEIE_R {
175        TXFIFOHEIE_R::new(((self.bits >> 14) & 1) != 0)
176    }
177    ///Bit 15 - Rx FIFO half full interrupt enable
178    #[inline(always)]
179    pub fn rxfifohfie(&self) -> RXFIFOHFIE_R {
180        RXFIFOHFIE_R::new(((self.bits >> 15) & 1) != 0)
181    }
182    ///Bit 16 - Tx FIFO full interrupt enable
183    #[inline(always)]
184    pub fn txfifofie(&self) -> TXFIFOFIE_R {
185        TXFIFOFIE_R::new(((self.bits >> 16) & 1) != 0)
186    }
187    ///Bit 17 - Rx FIFO full interrupt enable
188    #[inline(always)]
189    pub fn rxfifofie(&self) -> RXFIFOFIE_R {
190        RXFIFOFIE_R::new(((self.bits >> 17) & 1) != 0)
191    }
192    ///Bit 18 - Tx FIFO empty interrupt enable
193    #[inline(always)]
194    pub fn txfifoeie(&self) -> TXFIFOEIE_R {
195        TXFIFOEIE_R::new(((self.bits >> 18) & 1) != 0)
196    }
197    ///Bit 19 - Rx FIFO empty interrupt enable
198    #[inline(always)]
199    pub fn rxfifoeie(&self) -> RXFIFOEIE_R {
200        RXFIFOEIE_R::new(((self.bits >> 19) & 1) != 0)
201    }
202    ///Bit 20 - Data available in Tx FIFO interrupt enable
203    #[inline(always)]
204    pub fn txdavlie(&self) -> TXDAVLIE_R {
205        TXDAVLIE_R::new(((self.bits >> 20) & 1) != 0)
206    }
207    ///Bit 21 - Data available in Rx FIFO interrupt enable
208    #[inline(always)]
209    pub fn rxdavlie(&self) -> RXDAVLIE_R {
210        RXDAVLIE_R::new(((self.bits >> 21) & 1) != 0)
211    }
212    ///Bit 22 - SDIO mode interrupt received interrupt enable
213    #[inline(always)]
214    pub fn sdioitie(&self) -> SDIOITIE_R {
215        SDIOITIE_R::new(((self.bits >> 22) & 1) != 0)
216    }
217    ///Bit 23 - CE-ATA command completion signal received interrupt enable
218    #[inline(always)]
219    pub fn ceataendie(&self) -> CEATAENDIE_R {
220        CEATAENDIE_R::new(((self.bits >> 23) & 1) != 0)
221    }
222}
223impl core::fmt::Debug for R {
224    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
225        f.debug_struct("MASK")
226            .field("ceataendie", &self.ceataendie())
227            .field("sdioitie", &self.sdioitie())
228            .field("rxdavlie", &self.rxdavlie())
229            .field("txdavlie", &self.txdavlie())
230            .field("rxfifoeie", &self.rxfifoeie())
231            .field("txfifoeie", &self.txfifoeie())
232            .field("rxfifofie", &self.rxfifofie())
233            .field("txfifofie", &self.txfifofie())
234            .field("rxfifohfie", &self.rxfifohfie())
235            .field("txfifoheie", &self.txfifoheie())
236            .field("rxactie", &self.rxactie())
237            .field("txactie", &self.txactie())
238            .field("cmdactie", &self.cmdactie())
239            .field("dbckendie", &self.dbckendie())
240            .field("stbiterrie", &self.stbiterrie())
241            .field("dataendie", &self.dataendie())
242            .field("cmdsentie", &self.cmdsentie())
243            .field("cmdrendie", &self.cmdrendie())
244            .field("rxoverrie", &self.rxoverrie())
245            .field("txunderrie", &self.txunderrie())
246            .field("dtimeoutie", &self.dtimeoutie())
247            .field("ctimeoutie", &self.ctimeoutie())
248            .field("dcrcfailie", &self.dcrcfailie())
249            .field("ccrcfailie", &self.ccrcfailie())
250            .finish()
251    }
252}
253impl W {
254    ///Bit 0 - Command CRC fail interrupt enable
255    #[inline(always)]
256    pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<MASKrs> {
257        CCRCFAILIE_W::new(self, 0)
258    }
259    ///Bit 1 - Data CRC fail interrupt enable
260    #[inline(always)]
261    pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<MASKrs> {
262        DCRCFAILIE_W::new(self, 1)
263    }
264    ///Bit 2 - Command timeout interrupt enable
265    #[inline(always)]
266    pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<MASKrs> {
267        CTIMEOUTIE_W::new(self, 2)
268    }
269    ///Bit 3 - Data timeout interrupt enable
270    #[inline(always)]
271    pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<MASKrs> {
272        DTIMEOUTIE_W::new(self, 3)
273    }
274    ///Bit 4 - Tx FIFO underrun error interrupt enable
275    #[inline(always)]
276    pub fn txunderrie(&mut self) -> TXUNDERRIE_W<MASKrs> {
277        TXUNDERRIE_W::new(self, 4)
278    }
279    ///Bit 5 - Rx FIFO overrun error interrupt enable
280    #[inline(always)]
281    pub fn rxoverrie(&mut self) -> RXOVERRIE_W<MASKrs> {
282        RXOVERRIE_W::new(self, 5)
283    }
284    ///Bit 6 - Command response received interrupt enable
285    #[inline(always)]
286    pub fn cmdrendie(&mut self) -> CMDRENDIE_W<MASKrs> {
287        CMDRENDIE_W::new(self, 6)
288    }
289    ///Bit 7 - Command sent interrupt enable
290    #[inline(always)]
291    pub fn cmdsentie(&mut self) -> CMDSENTIE_W<MASKrs> {
292        CMDSENTIE_W::new(self, 7)
293    }
294    ///Bit 8 - Data end interrupt enable
295    #[inline(always)]
296    pub fn dataendie(&mut self) -> DATAENDIE_W<MASKrs> {
297        DATAENDIE_W::new(self, 8)
298    }
299    ///Bit 9 - Start bit error interrupt enable
300    #[inline(always)]
301    pub fn stbiterrie(&mut self) -> STBITERRIE_W<MASKrs> {
302        STBITERRIE_W::new(self, 9)
303    }
304    ///Bit 10 - Data block end interrupt enable
305    #[inline(always)]
306    pub fn dbckendie(&mut self) -> DBCKENDIE_W<MASKrs> {
307        DBCKENDIE_W::new(self, 10)
308    }
309    ///Bit 11 - Command acting interrupt enable
310    #[inline(always)]
311    pub fn cmdactie(&mut self) -> CMDACTIE_W<MASKrs> {
312        CMDACTIE_W::new(self, 11)
313    }
314    ///Bit 12 - Data transmit acting interrupt enable
315    #[inline(always)]
316    pub fn txactie(&mut self) -> TXACTIE_W<MASKrs> {
317        TXACTIE_W::new(self, 12)
318    }
319    ///Bit 13 - Data receive acting interrupt enable
320    #[inline(always)]
321    pub fn rxactie(&mut self) -> RXACTIE_W<MASKrs> {
322        RXACTIE_W::new(self, 13)
323    }
324    ///Bit 14 - Tx FIFO half empty interrupt enable
325    #[inline(always)]
326    pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<MASKrs> {
327        TXFIFOHEIE_W::new(self, 14)
328    }
329    ///Bit 15 - Rx FIFO half full interrupt enable
330    #[inline(always)]
331    pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<MASKrs> {
332        RXFIFOHFIE_W::new(self, 15)
333    }
334    ///Bit 16 - Tx FIFO full interrupt enable
335    #[inline(always)]
336    pub fn txfifofie(&mut self) -> TXFIFOFIE_W<MASKrs> {
337        TXFIFOFIE_W::new(self, 16)
338    }
339    ///Bit 17 - Rx FIFO full interrupt enable
340    #[inline(always)]
341    pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<MASKrs> {
342        RXFIFOFIE_W::new(self, 17)
343    }
344    ///Bit 18 - Tx FIFO empty interrupt enable
345    #[inline(always)]
346    pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<MASKrs> {
347        TXFIFOEIE_W::new(self, 18)
348    }
349    ///Bit 19 - Rx FIFO empty interrupt enable
350    #[inline(always)]
351    pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<MASKrs> {
352        RXFIFOEIE_W::new(self, 19)
353    }
354    ///Bit 20 - Data available in Tx FIFO interrupt enable
355    #[inline(always)]
356    pub fn txdavlie(&mut self) -> TXDAVLIE_W<MASKrs> {
357        TXDAVLIE_W::new(self, 20)
358    }
359    ///Bit 21 - Data available in Rx FIFO interrupt enable
360    #[inline(always)]
361    pub fn rxdavlie(&mut self) -> RXDAVLIE_W<MASKrs> {
362        RXDAVLIE_W::new(self, 21)
363    }
364    ///Bit 22 - SDIO mode interrupt received interrupt enable
365    #[inline(always)]
366    pub fn sdioitie(&mut self) -> SDIOITIE_W<MASKrs> {
367        SDIOITIE_W::new(self, 22)
368    }
369    ///Bit 23 - CE-ATA command completion signal received interrupt enable
370    #[inline(always)]
371    pub fn ceataendie(&mut self) -> CEATAENDIE_W<MASKrs> {
372        CEATAENDIE_W::new(self, 23)
373    }
374}
375/**mask register
376
377You can [`read`](crate::Reg::read) this register and get [`mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
378
379See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:MASK)*/
380pub struct MASKrs;
381impl crate::RegisterSpec for MASKrs {
382    type Ux = u32;
383}
384///`read()` method returns [`mask::R`](R) reader structure
385impl crate::Readable for MASKrs {}
386///`write(|w| ..)` method takes [`mask::W`](W) writer structure
387impl crate::Writable for MASKrs {
388    type Safety = crate::Unsafe;
389}
390///`reset()` method sets MASK to value 0
391impl crate::Resettable for MASKrs {}
stm32f1_staging/stm32f107/sdio/mask.rs

stm32f1_staging/stm32f107/sdio/
mask.rs
