stm32f1_staging/stm32f107/sdio/
icr.rs

1///Register `ICR` reader
2pub type R = crate::R<ICRrs>;
3///Register `ICR` writer
4pub type W = crate::W<ICRrs>;
5///Field `CCRCFAILC` reader - CCRCFAIL flag clear bit
6pub type CCRCFAILC_R = crate::BitReader;
7///Field `CCRCFAILC` writer - CCRCFAIL flag clear bit
8pub type CCRCFAILC_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DCRCFAILC` reader - DCRCFAIL flag clear bit
10pub type DCRCFAILC_R = crate::BitReader;
11///Field `DCRCFAILC` writer - DCRCFAIL flag clear bit
12pub type DCRCFAILC_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `CTIMEOUTC` reader - CTIMEOUT flag clear bit
14pub type CTIMEOUTC_R = crate::BitReader;
15///Field `CTIMEOUTC` writer - CTIMEOUT flag clear bit
16pub type CTIMEOUTC_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `DTIMEOUTC` reader - DTIMEOUT flag clear bit
18pub type DTIMEOUTC_R = crate::BitReader;
19///Field `DTIMEOUTC` writer - DTIMEOUT flag clear bit
20pub type DTIMEOUTC_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `TXUNDERRC` reader - TXUNDERR flag clear bit
22pub type TXUNDERRC_R = crate::BitReader;
23///Field `TXUNDERRC` writer - TXUNDERR flag clear bit
24pub type TXUNDERRC_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `RXOVERRC` reader - RXOVERR flag clear bit
26pub type RXOVERRC_R = crate::BitReader;
27///Field `RXOVERRC` writer - RXOVERR flag clear bit
28pub type RXOVERRC_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `CMDRENDC` reader - CMDREND flag clear bit
30pub type CMDRENDC_R = crate::BitReader;
31///Field `CMDRENDC` writer - CMDREND flag clear bit
32pub type CMDRENDC_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `CMDSENTC` reader - CMDSENT flag clear bit
34pub type CMDSENTC_R = crate::BitReader;
35///Field `CMDSENTC` writer - CMDSENT flag clear bit
36pub type CMDSENTC_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `DATAENDC` reader - DATAEND flag clear bit
38pub type DATAENDC_R = crate::BitReader;
39///Field `DATAENDC` writer - DATAEND flag clear bit
40pub type DATAENDC_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `STBITERRC` reader - STBITERR flag clear bit
42pub type STBITERRC_R = crate::BitReader;
43///Field `STBITERRC` writer - STBITERR flag clear bit
44pub type STBITERRC_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `DBCKENDC` reader - DBCKEND flag clear bit
46pub type DBCKENDC_R = crate::BitReader;
47///Field `DBCKENDC` writer - DBCKEND flag clear bit
48pub type DBCKENDC_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `SDIOITC` reader - SDIOIT flag clear bit
50pub type SDIOITC_R = crate::BitReader;
51///Field `SDIOITC` writer - SDIOIT flag clear bit
52pub type SDIOITC_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `CEATAENDC` reader - CEATAEND flag clear bit
54pub type CEATAENDC_R = crate::BitReader;
55///Field `CEATAENDC` writer - CEATAEND flag clear bit
56pub type CEATAENDC_W<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58    ///Bit 0 - CCRCFAIL flag clear bit
59    #[inline(always)]
60    pub fn ccrcfailc(&self) -> CCRCFAILC_R {
61        CCRCFAILC_R::new((self.bits & 1) != 0)
62    }
63    ///Bit 1 - DCRCFAIL flag clear bit
64    #[inline(always)]
65    pub fn dcrcfailc(&self) -> DCRCFAILC_R {
66        DCRCFAILC_R::new(((self.bits >> 1) & 1) != 0)
67    }
68    ///Bit 2 - CTIMEOUT flag clear bit
69    #[inline(always)]
70    pub fn ctimeoutc(&self) -> CTIMEOUTC_R {
71        CTIMEOUTC_R::new(((self.bits >> 2) & 1) != 0)
72    }
73    ///Bit 3 - DTIMEOUT flag clear bit
74    #[inline(always)]
75    pub fn dtimeoutc(&self) -> DTIMEOUTC_R {
76        DTIMEOUTC_R::new(((self.bits >> 3) & 1) != 0)
77    }
78    ///Bit 4 - TXUNDERR flag clear bit
79    #[inline(always)]
80    pub fn txunderrc(&self) -> TXUNDERRC_R {
81        TXUNDERRC_R::new(((self.bits >> 4) & 1) != 0)
82    }
83    ///Bit 5 - RXOVERR flag clear bit
84    #[inline(always)]
85    pub fn rxoverrc(&self) -> RXOVERRC_R {
86        RXOVERRC_R::new(((self.bits >> 5) & 1) != 0)
87    }
88    ///Bit 6 - CMDREND flag clear bit
89    #[inline(always)]
90    pub fn cmdrendc(&self) -> CMDRENDC_R {
91        CMDRENDC_R::new(((self.bits >> 6) & 1) != 0)
92    }
93    ///Bit 7 - CMDSENT flag clear bit
94    #[inline(always)]
95    pub fn cmdsentc(&self) -> CMDSENTC_R {
96        CMDSENTC_R::new(((self.bits >> 7) & 1) != 0)
97    }
98    ///Bit 8 - DATAEND flag clear bit
99    #[inline(always)]
100    pub fn dataendc(&self) -> DATAENDC_R {
101        DATAENDC_R::new(((self.bits >> 8) & 1) != 0)
102    }
103    ///Bit 9 - STBITERR flag clear bit
104    #[inline(always)]
105    pub fn stbiterrc(&self) -> STBITERRC_R {
106        STBITERRC_R::new(((self.bits >> 9) & 1) != 0)
107    }
108    ///Bit 10 - DBCKEND flag clear bit
109    #[inline(always)]
110    pub fn dbckendc(&self) -> DBCKENDC_R {
111        DBCKENDC_R::new(((self.bits >> 10) & 1) != 0)
112    }
113    ///Bit 22 - SDIOIT flag clear bit
114    #[inline(always)]
115    pub fn sdioitc(&self) -> SDIOITC_R {
116        SDIOITC_R::new(((self.bits >> 22) & 1) != 0)
117    }
118    ///Bit 23 - CEATAEND flag clear bit
119    #[inline(always)]
120    pub fn ceataendc(&self) -> CEATAENDC_R {
121        CEATAENDC_R::new(((self.bits >> 23) & 1) != 0)
122    }
123}
124impl core::fmt::Debug for R {
125    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
126        f.debug_struct("ICR")
127            .field("ceataendc", &self.ceataendc())
128            .field("sdioitc", &self.sdioitc())
129            .field("dbckendc", &self.dbckendc())
130            .field("stbiterrc", &self.stbiterrc())
131            .field("dataendc", &self.dataendc())
132            .field("cmdsentc", &self.cmdsentc())
133            .field("cmdrendc", &self.cmdrendc())
134            .field("rxoverrc", &self.rxoverrc())
135            .field("txunderrc", &self.txunderrc())
136            .field("dtimeoutc", &self.dtimeoutc())
137            .field("ctimeoutc", &self.ctimeoutc())
138            .field("dcrcfailc", &self.dcrcfailc())
139            .field("ccrcfailc", &self.ccrcfailc())
140            .finish()
141    }
142}
143impl W {
144    ///Bit 0 - CCRCFAIL flag clear bit
145    #[inline(always)]
146    pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<ICRrs> {
147        CCRCFAILC_W::new(self, 0)
148    }
149    ///Bit 1 - DCRCFAIL flag clear bit
150    #[inline(always)]
151    pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<ICRrs> {
152        DCRCFAILC_W::new(self, 1)
153    }
154    ///Bit 2 - CTIMEOUT flag clear bit
155    #[inline(always)]
156    pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<ICRrs> {
157        CTIMEOUTC_W::new(self, 2)
158    }
159    ///Bit 3 - DTIMEOUT flag clear bit
160    #[inline(always)]
161    pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<ICRrs> {
162        DTIMEOUTC_W::new(self, 3)
163    }
164    ///Bit 4 - TXUNDERR flag clear bit
165    #[inline(always)]
166    pub fn txunderrc(&mut self) -> TXUNDERRC_W<ICRrs> {
167        TXUNDERRC_W::new(self, 4)
168    }
169    ///Bit 5 - RXOVERR flag clear bit
170    #[inline(always)]
171    pub fn rxoverrc(&mut self) -> RXOVERRC_W<ICRrs> {
172        RXOVERRC_W::new(self, 5)
173    }
174    ///Bit 6 - CMDREND flag clear bit
175    #[inline(always)]
176    pub fn cmdrendc(&mut self) -> CMDRENDC_W<ICRrs> {
177        CMDRENDC_W::new(self, 6)
178    }
179    ///Bit 7 - CMDSENT flag clear bit
180    #[inline(always)]
181    pub fn cmdsentc(&mut self) -> CMDSENTC_W<ICRrs> {
182        CMDSENTC_W::new(self, 7)
183    }
184    ///Bit 8 - DATAEND flag clear bit
185    #[inline(always)]
186    pub fn dataendc(&mut self) -> DATAENDC_W<ICRrs> {
187        DATAENDC_W::new(self, 8)
188    }
189    ///Bit 9 - STBITERR flag clear bit
190    #[inline(always)]
191    pub fn stbiterrc(&mut self) -> STBITERRC_W<ICRrs> {
192        STBITERRC_W::new(self, 9)
193    }
194    ///Bit 10 - DBCKEND flag clear bit
195    #[inline(always)]
196    pub fn dbckendc(&mut self) -> DBCKENDC_W<ICRrs> {
197        DBCKENDC_W::new(self, 10)
198    }
199    ///Bit 22 - SDIOIT flag clear bit
200    #[inline(always)]
201    pub fn sdioitc(&mut self) -> SDIOITC_W<ICRrs> {
202        SDIOITC_W::new(self, 22)
203    }
204    ///Bit 23 - CEATAEND flag clear bit
205    #[inline(always)]
206    pub fn ceataendc(&mut self) -> CEATAENDC_W<ICRrs> {
207        CEATAENDC_W::new(self, 23)
208    }
209}
210/**interrupt clear register
211
212You can [`read`](crate::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
213
214See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:ICR)*/
215pub struct ICRrs;
216impl crate::RegisterSpec for ICRrs {
217    type Ux = u32;
218}
219///`read()` method returns [`icr::R`](R) reader structure
220impl crate::Readable for ICRrs {}
221///`write(|w| ..)` method takes [`icr::W`](W) writer structure
222impl crate::Writable for ICRrs {
223    type Safety = crate::Unsafe;
224}
225///`reset()` method sets ICR to value 0
226impl crate::Resettable for ICRrs {}
stm32f1_staging/stm32f107/sdio/icr.rs

stm32f1_staging/stm32f107/sdio/
icr.rs
