stm32f1_staging/stm32f107/rcc/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**Internal High Speed clock enable
6
7Value on reset: 1*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum HSION {
11    ///0: Clock Off
12    Off = 0,
13    ///1: Clock On
14    On = 1,
15}
16impl From<HSION> for bool {
17    #[inline(always)]
18    fn from(variant: HSION) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `HSION` reader - Internal High Speed clock enable
23pub type HSION_R = crate::BitReader<HSION>;
24impl HSION_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> HSION {
28        match self.bits {
29            false => HSION::Off,
30            true => HSION::On,
31        }
32    }
33    ///Clock Off
34    #[inline(always)]
35    pub fn is_off(&self) -> bool {
36        *self == HSION::Off
37    }
38    ///Clock On
39    #[inline(always)]
40    pub fn is_on(&self) -> bool {
41        *self == HSION::On
42    }
43}
44///Field `HSION` writer - Internal High Speed clock enable
45pub type HSION_W<'a, REG> = crate::BitWriter<'a, REG, HSION>;
46impl<'a, REG> HSION_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Clock Off
51    #[inline(always)]
52    pub fn off(self) -> &'a mut crate::W<REG> {
53        self.variant(HSION::Off)
54    }
55    ///Clock On
56    #[inline(always)]
57    pub fn on(self) -> &'a mut crate::W<REG> {
58        self.variant(HSION::On)
59    }
60}
61/**Internal High Speed clock ready flag
62
63Value on reset: 1*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum HSIRDYR {
67    ///0: Clock not ready
68    NotReady = 0,
69    ///1: Clock ready
70    Ready = 1,
71}
72impl From<HSIRDYR> for bool {
73    #[inline(always)]
74    fn from(variant: HSIRDYR) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `HSIRDY` reader - Internal High Speed clock ready flag
79pub type HSIRDY_R = crate::BitReader<HSIRDYR>;
80impl HSIRDY_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> HSIRDYR {
84        match self.bits {
85            false => HSIRDYR::NotReady,
86            true => HSIRDYR::Ready,
87        }
88    }
89    ///Clock not ready
90    #[inline(always)]
91    pub fn is_not_ready(&self) -> bool {
92        *self == HSIRDYR::NotReady
93    }
94    ///Clock ready
95    #[inline(always)]
96    pub fn is_ready(&self) -> bool {
97        *self == HSIRDYR::Ready
98    }
99}
100///Field `HSITRIM` reader - Internal High Speed clock trimming
101pub type HSITRIM_R = crate::FieldReader;
102///Field `HSITRIM` writer - Internal High Speed clock trimming
103pub type HSITRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 5, u8, crate::Safe>;
104///Field `HSICAL` reader - Internal High Speed clock Calibration
105pub type HSICAL_R = crate::FieldReader;
106///Field `HSEON` reader - External High Speed clock enable
107pub use HSION_R as HSEON_R;
108///Field `HSEON` writer - External High Speed clock enable
109pub use HSION_W as HSEON_W;
110///Field `HSERDY` reader - External High Speed clock ready flag
111pub use HSIRDY_R as HSERDY_R;
112/**External High Speed clock Bypass
113
114Value on reset: 0*/
115#[cfg_attr(feature = "defmt", derive(defmt::Format))]
116#[derive(Clone, Copy, Debug, PartialEq, Eq)]
117pub enum HSEBYP {
118    ///0: HSE crystal oscillator not bypassed
119    NotBypassed = 0,
120    ///1: HSE crystal oscillator bypassed with external clock
121    Bypassed = 1,
122}
123impl From<HSEBYP> for bool {
124    #[inline(always)]
125    fn from(variant: HSEBYP) -> Self {
126        variant as u8 != 0
127    }
128}
129///Field `HSEBYP` reader - External High Speed clock Bypass
130pub type HSEBYP_R = crate::BitReader<HSEBYP>;
131impl HSEBYP_R {
132    ///Get enumerated values variant
133    #[inline(always)]
134    pub const fn variant(&self) -> HSEBYP {
135        match self.bits {
136            false => HSEBYP::NotBypassed,
137            true => HSEBYP::Bypassed,
138        }
139    }
140    ///HSE crystal oscillator not bypassed
141    #[inline(always)]
142    pub fn is_not_bypassed(&self) -> bool {
143        *self == HSEBYP::NotBypassed
144    }
145    ///HSE crystal oscillator bypassed with external clock
146    #[inline(always)]
147    pub fn is_bypassed(&self) -> bool {
148        *self == HSEBYP::Bypassed
149    }
150}
151///Field `HSEBYP` writer - External High Speed clock Bypass
152pub type HSEBYP_W<'a, REG> = crate::BitWriter<'a, REG, HSEBYP>;
153impl<'a, REG> HSEBYP_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156{
157    ///HSE crystal oscillator not bypassed
158    #[inline(always)]
159    pub fn not_bypassed(self) -> &'a mut crate::W<REG> {
160        self.variant(HSEBYP::NotBypassed)
161    }
162    ///HSE crystal oscillator bypassed with external clock
163    #[inline(always)]
164    pub fn bypassed(self) -> &'a mut crate::W<REG> {
165        self.variant(HSEBYP::Bypassed)
166    }
167}
168/**Clock Security System enable
169
170Value on reset: 0*/
171#[cfg_attr(feature = "defmt", derive(defmt::Format))]
172#[derive(Clone, Copy, Debug, PartialEq, Eq)]
173pub enum CSSON {
174    ///0: Clock security system disabled (clock detector OFF)
175    Off = 0,
176    ///1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
177    On = 1,
178}
179impl From<CSSON> for bool {
180    #[inline(always)]
181    fn from(variant: CSSON) -> Self {
182        variant as u8 != 0
183    }
184}
185///Field `CSSON` reader - Clock Security System enable
186pub type CSSON_R = crate::BitReader<CSSON>;
187impl CSSON_R {
188    ///Get enumerated values variant
189    #[inline(always)]
190    pub const fn variant(&self) -> CSSON {
191        match self.bits {
192            false => CSSON::Off,
193            true => CSSON::On,
194        }
195    }
196    ///Clock security system disabled (clock detector OFF)
197    #[inline(always)]
198    pub fn is_off(&self) -> bool {
199        *self == CSSON::Off
200    }
201    ///Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
202    #[inline(always)]
203    pub fn is_on(&self) -> bool {
204        *self == CSSON::On
205    }
206}
207///Field `CSSON` writer - Clock Security System enable
208pub type CSSON_W<'a, REG> = crate::BitWriter<'a, REG, CSSON>;
209impl<'a, REG> CSSON_W<'a, REG>
210where
211    REG: crate::Writable + crate::RegisterSpec,
212{
213    ///Clock security system disabled (clock detector OFF)
214    #[inline(always)]
215    pub fn off(self) -> &'a mut crate::W<REG> {
216        self.variant(CSSON::Off)
217    }
218    ///Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
219    #[inline(always)]
220    pub fn on(self) -> &'a mut crate::W<REG> {
221        self.variant(CSSON::On)
222    }
223}
224///Field `PLLON` reader - PLL enable
225pub use HSION_R as PLLON_R;
226///Field `PLLON` writer - PLL enable
227pub use HSION_W as PLLON_W;
228///Field `PLLRDY` reader - PLL clock ready flag
229pub use HSIRDY_R as PLLRDY_R;
230///Field `PLL2ON` reader - PLL2 enable
231pub type PLL2ON_R = crate::BitReader;
232///Field `PLL2ON` writer - PLL2 enable
233pub type PLL2ON_W<'a, REG> = crate::BitWriter<'a, REG>;
234///Field `PLL2RDY` reader - PLL2 clock ready flag
235pub use HSIRDY_R as PLL2RDY_R;
236///Field `PLL3ON` reader - PLL3 enable
237pub type PLL3ON_R = crate::BitReader;
238///Field `PLL3ON` writer - PLL3 enable
239pub type PLL3ON_W<'a, REG> = crate::BitWriter<'a, REG>;
240///Field `PLL3RDY` reader - PLL3 clock ready flag
241pub use HSIRDY_R as PLL3RDY_R;
242impl R {
243    ///Bit 0 - Internal High Speed clock enable
244    #[inline(always)]
245    pub fn hsion(&self) -> HSION_R {
246        HSION_R::new((self.bits & 1) != 0)
247    }
248    ///Bit 1 - Internal High Speed clock ready flag
249    #[inline(always)]
250    pub fn hsirdy(&self) -> HSIRDY_R {
251        HSIRDY_R::new(((self.bits >> 1) & 1) != 0)
252    }
253    ///Bits 3:7 - Internal High Speed clock trimming
254    #[inline(always)]
255    pub fn hsitrim(&self) -> HSITRIM_R {
256        HSITRIM_R::new(((self.bits >> 3) & 0x1f) as u8)
257    }
258    ///Bits 8:15 - Internal High Speed clock Calibration
259    #[inline(always)]
260    pub fn hsical(&self) -> HSICAL_R {
261        HSICAL_R::new(((self.bits >> 8) & 0xff) as u8)
262    }
263    ///Bit 16 - External High Speed clock enable
264    #[inline(always)]
265    pub fn hseon(&self) -> HSEON_R {
266        HSEON_R::new(((self.bits >> 16) & 1) != 0)
267    }
268    ///Bit 17 - External High Speed clock ready flag
269    #[inline(always)]
270    pub fn hserdy(&self) -> HSERDY_R {
271        HSERDY_R::new(((self.bits >> 17) & 1) != 0)
272    }
273    ///Bit 18 - External High Speed clock Bypass
274    #[inline(always)]
275    pub fn hsebyp(&self) -> HSEBYP_R {
276        HSEBYP_R::new(((self.bits >> 18) & 1) != 0)
277    }
278    ///Bit 19 - Clock Security System enable
279    #[inline(always)]
280    pub fn csson(&self) -> CSSON_R {
281        CSSON_R::new(((self.bits >> 19) & 1) != 0)
282    }
283    ///Bit 24 - PLL enable
284    #[inline(always)]
285    pub fn pllon(&self) -> PLLON_R {
286        PLLON_R::new(((self.bits >> 24) & 1) != 0)
287    }
288    ///Bit 25 - PLL clock ready flag
289    #[inline(always)]
290    pub fn pllrdy(&self) -> PLLRDY_R {
291        PLLRDY_R::new(((self.bits >> 25) & 1) != 0)
292    }
293    ///Bit 26 - PLL2 enable
294    #[inline(always)]
295    pub fn pll2on(&self) -> PLL2ON_R {
296        PLL2ON_R::new(((self.bits >> 26) & 1) != 0)
297    }
298    ///Bit 27 - PLL2 clock ready flag
299    #[inline(always)]
300    pub fn pll2rdy(&self) -> PLL2RDY_R {
301        PLL2RDY_R::new(((self.bits >> 27) & 1) != 0)
302    }
303    ///Bit 28 - PLL3 enable
304    #[inline(always)]
305    pub fn pll3on(&self) -> PLL3ON_R {
306        PLL3ON_R::new(((self.bits >> 28) & 1) != 0)
307    }
308    ///Bit 29 - PLL3 clock ready flag
309    #[inline(always)]
310    pub fn pll3rdy(&self) -> PLL3RDY_R {
311        PLL3RDY_R::new(((self.bits >> 29) & 1) != 0)
312    }
313}
314impl core::fmt::Debug for R {
315    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
316        f.debug_struct("CR")
317            .field("hsion", &self.hsion())
318            .field("hsirdy", &self.hsirdy())
319            .field("hsitrim", &self.hsitrim())
320            .field("hsical", &self.hsical())
321            .field("hseon", &self.hseon())
322            .field("hserdy", &self.hserdy())
323            .field("hsebyp", &self.hsebyp())
324            .field("csson", &self.csson())
325            .field("pllon", &self.pllon())
326            .field("pllrdy", &self.pllrdy())
327            .field("pll2on", &self.pll2on())
328            .field("pll2rdy", &self.pll2rdy())
329            .field("pll3on", &self.pll3on())
330            .field("pll3rdy", &self.pll3rdy())
331            .finish()
332    }
333}
334impl W {
335    ///Bit 0 - Internal High Speed clock enable
336    #[inline(always)]
337    pub fn hsion(&mut self) -> HSION_W<CRrs> {
338        HSION_W::new(self, 0)
339    }
340    ///Bits 3:7 - Internal High Speed clock trimming
341    #[inline(always)]
342    pub fn hsitrim(&mut self) -> HSITRIM_W<CRrs> {
343        HSITRIM_W::new(self, 3)
344    }
345    ///Bit 16 - External High Speed clock enable
346    #[inline(always)]
347    pub fn hseon(&mut self) -> HSEON_W<CRrs> {
348        HSEON_W::new(self, 16)
349    }
350    ///Bit 18 - External High Speed clock Bypass
351    #[inline(always)]
352    pub fn hsebyp(&mut self) -> HSEBYP_W<CRrs> {
353        HSEBYP_W::new(self, 18)
354    }
355    ///Bit 19 - Clock Security System enable
356    #[inline(always)]
357    pub fn csson(&mut self) -> CSSON_W<CRrs> {
358        CSSON_W::new(self, 19)
359    }
360    ///Bit 24 - PLL enable
361    #[inline(always)]
362    pub fn pllon(&mut self) -> PLLON_W<CRrs> {
363        PLLON_W::new(self, 24)
364    }
365    ///Bit 26 - PLL2 enable
366    #[inline(always)]
367    pub fn pll2on(&mut self) -> PLL2ON_W<CRrs> {
368        PLL2ON_W::new(self, 26)
369    }
370    ///Bit 28 - PLL3 enable
371    #[inline(always)]
372    pub fn pll3on(&mut self) -> PLL3ON_W<CRrs> {
373        PLL3ON_W::new(self, 28)
374    }
375}
376/**Clock control register
377
378You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
379
380See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:CR)*/
381pub struct CRrs;
382impl crate::RegisterSpec for CRrs {
383    type Ux = u32;
384}
385///`read()` method returns [`cr::R`](R) reader structure
386impl crate::Readable for CRrs {}
387///`write(|w| ..)` method takes [`cr::W`](W) writer structure
388impl crate::Writable for CRrs {
389    type Safety = crate::Unsafe;
390}
391///`reset()` method sets CR to value 0x83
392impl crate::Resettable for CRrs {
393    const RESET_VALUE: u32 = 0x83;
394}
stm32f1_staging/stm32f107/rcc/cr.rs

stm32f1_staging/stm32f107/rcc/
cr.rs
