stm32f1_staging/stm32f107/rcc/
cir.rs

1///Register `CIR` reader
2pub type R = crate::R<CIRrs>;
3///Register `CIR` writer
4pub type W = crate::W<CIRrs>;
5/**LSI Ready Interrupt flag
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum LSIRDYFR {
11    ///0: No clock ready interrupt
12    NotInterrupted = 0,
13    ///1: Clock ready interrupt
14    Interrupted = 1,
15}
16impl From<LSIRDYFR> for bool {
17    #[inline(always)]
18    fn from(variant: LSIRDYFR) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `LSIRDYF` reader - LSI Ready Interrupt flag
23pub type LSIRDYF_R = crate::BitReader<LSIRDYFR>;
24impl LSIRDYF_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> LSIRDYFR {
28        match self.bits {
29            false => LSIRDYFR::NotInterrupted,
30            true => LSIRDYFR::Interrupted,
31        }
32    }
33    ///No clock ready interrupt
34    #[inline(always)]
35    pub fn is_not_interrupted(&self) -> bool {
36        *self == LSIRDYFR::NotInterrupted
37    }
38    ///Clock ready interrupt
39    #[inline(always)]
40    pub fn is_interrupted(&self) -> bool {
41        *self == LSIRDYFR::Interrupted
42    }
43}
44///Field `LSERDYF` reader - LSE Ready Interrupt flag
45pub use LSIRDYF_R as LSERDYF_R;
46///Field `HSIRDYF` reader - HSI Ready Interrupt flag
47pub use LSIRDYF_R as HSIRDYF_R;
48///Field `HSERDYF` reader - HSE Ready Interrupt flag
49pub use LSIRDYF_R as HSERDYF_R;
50///Field `PLLRDYF` reader - PLL Ready Interrupt flag
51pub use LSIRDYF_R as PLLRDYF_R;
52///Field `PLL2RDYF` reader - PLL2 Ready Interrupt flag
53pub use LSIRDYF_R as PLL2RDYF_R;
54///Field `PLL3RDYF` reader - PLL3 Ready Interrupt flag
55pub use LSIRDYF_R as PLL3RDYF_R;
56/**Clock Security System Interrupt flag
57
58Value on reset: 0*/
59#[cfg_attr(feature = "defmt", derive(defmt::Format))]
60#[derive(Clone, Copy, Debug, PartialEq, Eq)]
61pub enum CSSFR {
62    ///0: No clock security interrupt caused by HSE clock failure
63    NotInterrupted = 0,
64    ///1: Clock security interrupt caused by HSE clock failure
65    Interrupted = 1,
66}
67impl From<CSSFR> for bool {
68    #[inline(always)]
69    fn from(variant: CSSFR) -> Self {
70        variant as u8 != 0
71    }
72}
73///Field `CSSF` reader - Clock Security System Interrupt flag
74pub type CSSF_R = crate::BitReader<CSSFR>;
75impl CSSF_R {
76    ///Get enumerated values variant
77    #[inline(always)]
78    pub const fn variant(&self) -> CSSFR {
79        match self.bits {
80            false => CSSFR::NotInterrupted,
81            true => CSSFR::Interrupted,
82        }
83    }
84    ///No clock security interrupt caused by HSE clock failure
85    #[inline(always)]
86    pub fn is_not_interrupted(&self) -> bool {
87        *self == CSSFR::NotInterrupted
88    }
89    ///Clock security interrupt caused by HSE clock failure
90    #[inline(always)]
91    pub fn is_interrupted(&self) -> bool {
92        *self == CSSFR::Interrupted
93    }
94}
95/**LSI Ready Interrupt Enable
96
97Value on reset: 0*/
98#[cfg_attr(feature = "defmt", derive(defmt::Format))]
99#[derive(Clone, Copy, Debug, PartialEq, Eq)]
100pub enum LSIRDYIE {
101    ///0: Interrupt disabled
102    Disabled = 0,
103    ///1: Interrupt enabled
104    Enabled = 1,
105}
106impl From<LSIRDYIE> for bool {
107    #[inline(always)]
108    fn from(variant: LSIRDYIE) -> Self {
109        variant as u8 != 0
110    }
111}
112///Field `LSIRDYIE` reader - LSI Ready Interrupt Enable
113pub type LSIRDYIE_R = crate::BitReader<LSIRDYIE>;
114impl LSIRDYIE_R {
115    ///Get enumerated values variant
116    #[inline(always)]
117    pub const fn variant(&self) -> LSIRDYIE {
118        match self.bits {
119            false => LSIRDYIE::Disabled,
120            true => LSIRDYIE::Enabled,
121        }
122    }
123    ///Interrupt disabled
124    #[inline(always)]
125    pub fn is_disabled(&self) -> bool {
126        *self == LSIRDYIE::Disabled
127    }
128    ///Interrupt enabled
129    #[inline(always)]
130    pub fn is_enabled(&self) -> bool {
131        *self == LSIRDYIE::Enabled
132    }
133}
134///Field `LSIRDYIE` writer - LSI Ready Interrupt Enable
135pub type LSIRDYIE_W<'a, REG> = crate::BitWriter<'a, REG, LSIRDYIE>;
136impl<'a, REG> LSIRDYIE_W<'a, REG>
137where
138    REG: crate::Writable + crate::RegisterSpec,
139{
140    ///Interrupt disabled
141    #[inline(always)]
142    pub fn disabled(self) -> &'a mut crate::W<REG> {
143        self.variant(LSIRDYIE::Disabled)
144    }
145    ///Interrupt enabled
146    #[inline(always)]
147    pub fn enabled(self) -> &'a mut crate::W<REG> {
148        self.variant(LSIRDYIE::Enabled)
149    }
150}
151///Field `LSERDYIE` reader - LSE Ready Interrupt Enable
152pub use LSIRDYIE_R as LSERDYIE_R;
153///Field `HSIRDYIE` reader - HSI Ready Interrupt Enable
154pub use LSIRDYIE_R as HSIRDYIE_R;
155///Field `HSERDYIE` reader - HSE Ready Interrupt Enable
156pub use LSIRDYIE_R as HSERDYIE_R;
157///Field `PLLRDYIE` reader - PLL Ready Interrupt Enable
158pub use LSIRDYIE_R as PLLRDYIE_R;
159///Field `PLL2RDYIE` reader - PLL2 Ready Interrupt Enable
160pub use LSIRDYIE_R as PLL2RDYIE_R;
161///Field `PLL3RDYIE` reader - PLL3 Ready Interrupt Enable
162pub use LSIRDYIE_R as PLL3RDYIE_R;
163///Field `LSERDYIE` writer - LSE Ready Interrupt Enable
164pub use LSIRDYIE_W as LSERDYIE_W;
165///Field `HSIRDYIE` writer - HSI Ready Interrupt Enable
166pub use LSIRDYIE_W as HSIRDYIE_W;
167///Field `HSERDYIE` writer - HSE Ready Interrupt Enable
168pub use LSIRDYIE_W as HSERDYIE_W;
169///Field `PLLRDYIE` writer - PLL Ready Interrupt Enable
170pub use LSIRDYIE_W as PLLRDYIE_W;
171///Field `PLL2RDYIE` writer - PLL2 Ready Interrupt Enable
172pub use LSIRDYIE_W as PLL2RDYIE_W;
173///Field `PLL3RDYIE` writer - PLL3 Ready Interrupt Enable
174pub use LSIRDYIE_W as PLL3RDYIE_W;
175/**LSI Ready Interrupt Clear
176
177Value on reset: 0*/
178#[cfg_attr(feature = "defmt", derive(defmt::Format))]
179#[derive(Clone, Copy, Debug, PartialEq, Eq)]
180pub enum LSIRDYCW {
181    ///1: Clear interrupt flag
182    Clear = 1,
183}
184impl From<LSIRDYCW> for bool {
185    #[inline(always)]
186    fn from(variant: LSIRDYCW) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `LSIRDYC` writer - LSI Ready Interrupt Clear
191pub type LSIRDYC_W<'a, REG> = crate::BitWriter<'a, REG, LSIRDYCW>;
192impl<'a, REG> LSIRDYC_W<'a, REG>
193where
194    REG: crate::Writable + crate::RegisterSpec,
195{
196    ///Clear interrupt flag
197    #[inline(always)]
198    pub fn clear(self) -> &'a mut crate::W<REG> {
199        self.variant(LSIRDYCW::Clear)
200    }
201}
202///Field `LSERDYC` writer - LSE Ready Interrupt Clear
203pub use LSIRDYC_W as LSERDYC_W;
204///Field `HSIRDYC` writer - HSI Ready Interrupt Clear
205pub use LSIRDYC_W as HSIRDYC_W;
206///Field `HSERDYC` writer - HSE Ready Interrupt Clear
207pub use LSIRDYC_W as HSERDYC_W;
208///Field `PLLRDYC` writer - PLL Ready Interrupt Clear
209pub use LSIRDYC_W as PLLRDYC_W;
210///Field `PLL2RDYC` writer - PLL2 Ready Interrupt Clear
211pub use LSIRDYC_W as PLL2RDYC_W;
212///Field `PLL3RDYC` writer - PLL3 Ready Interrupt Clear
213pub use LSIRDYC_W as PLL3RDYC_W;
214/**Clock security system interrupt clear
215
216Value on reset: 0*/
217#[cfg_attr(feature = "defmt", derive(defmt::Format))]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219pub enum CSSCW {
220    ///1: Clear CSSF flag
221    Clear = 1,
222}
223impl From<CSSCW> for bool {
224    #[inline(always)]
225    fn from(variant: CSSCW) -> Self {
226        variant as u8 != 0
227    }
228}
229///Field `CSSC` writer - Clock security system interrupt clear
230pub type CSSC_W<'a, REG> = crate::BitWriter<'a, REG, CSSCW>;
231impl<'a, REG> CSSC_W<'a, REG>
232where
233    REG: crate::Writable + crate::RegisterSpec,
234{
235    ///Clear CSSF flag
236    #[inline(always)]
237    pub fn clear(self) -> &'a mut crate::W<REG> {
238        self.variant(CSSCW::Clear)
239    }
240}
241impl R {
242    ///Bit 0 - LSI Ready Interrupt flag
243    #[inline(always)]
244    pub fn lsirdyf(&self) -> LSIRDYF_R {
245        LSIRDYF_R::new((self.bits & 1) != 0)
246    }
247    ///Bit 1 - LSE Ready Interrupt flag
248    #[inline(always)]
249    pub fn lserdyf(&self) -> LSERDYF_R {
250        LSERDYF_R::new(((self.bits >> 1) & 1) != 0)
251    }
252    ///Bit 2 - HSI Ready Interrupt flag
253    #[inline(always)]
254    pub fn hsirdyf(&self) -> HSIRDYF_R {
255        HSIRDYF_R::new(((self.bits >> 2) & 1) != 0)
256    }
257    ///Bit 3 - HSE Ready Interrupt flag
258    #[inline(always)]
259    pub fn hserdyf(&self) -> HSERDYF_R {
260        HSERDYF_R::new(((self.bits >> 3) & 1) != 0)
261    }
262    ///Bit 4 - PLL Ready Interrupt flag
263    #[inline(always)]
264    pub fn pllrdyf(&self) -> PLLRDYF_R {
265        PLLRDYF_R::new(((self.bits >> 4) & 1) != 0)
266    }
267    ///Bit 5 - PLL2 Ready Interrupt flag
268    #[inline(always)]
269    pub fn pll2rdyf(&self) -> PLL2RDYF_R {
270        PLL2RDYF_R::new(((self.bits >> 5) & 1) != 0)
271    }
272    ///Bit 6 - PLL3 Ready Interrupt flag
273    #[inline(always)]
274    pub fn pll3rdyf(&self) -> PLL3RDYF_R {
275        PLL3RDYF_R::new(((self.bits >> 6) & 1) != 0)
276    }
277    ///Bit 7 - Clock Security System Interrupt flag
278    #[inline(always)]
279    pub fn cssf(&self) -> CSSF_R {
280        CSSF_R::new(((self.bits >> 7) & 1) != 0)
281    }
282    ///Bit 8 - LSI Ready Interrupt Enable
283    #[inline(always)]
284    pub fn lsirdyie(&self) -> LSIRDYIE_R {
285        LSIRDYIE_R::new(((self.bits >> 8) & 1) != 0)
286    }
287    ///Bit 9 - LSE Ready Interrupt Enable
288    #[inline(always)]
289    pub fn lserdyie(&self) -> LSERDYIE_R {
290        LSERDYIE_R::new(((self.bits >> 9) & 1) != 0)
291    }
292    ///Bit 10 - HSI Ready Interrupt Enable
293    #[inline(always)]
294    pub fn hsirdyie(&self) -> HSIRDYIE_R {
295        HSIRDYIE_R::new(((self.bits >> 10) & 1) != 0)
296    }
297    ///Bit 11 - HSE Ready Interrupt Enable
298    #[inline(always)]
299    pub fn hserdyie(&self) -> HSERDYIE_R {
300        HSERDYIE_R::new(((self.bits >> 11) & 1) != 0)
301    }
302    ///Bit 12 - PLL Ready Interrupt Enable
303    #[inline(always)]
304    pub fn pllrdyie(&self) -> PLLRDYIE_R {
305        PLLRDYIE_R::new(((self.bits >> 12) & 1) != 0)
306    }
307    ///Bit 13 - PLL2 Ready Interrupt Enable
308    #[inline(always)]
309    pub fn pll2rdyie(&self) -> PLL2RDYIE_R {
310        PLL2RDYIE_R::new(((self.bits >> 13) & 1) != 0)
311    }
312    ///Bit 14 - PLL3 Ready Interrupt Enable
313    #[inline(always)]
314    pub fn pll3rdyie(&self) -> PLL3RDYIE_R {
315        PLL3RDYIE_R::new(((self.bits >> 14) & 1) != 0)
316    }
317}
318impl core::fmt::Debug for R {
319    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
320        f.debug_struct("CIR")
321            .field("lsirdyf", &self.lsirdyf())
322            .field("lserdyf", &self.lserdyf())
323            .field("hsirdyf", &self.hsirdyf())
324            .field("hserdyf", &self.hserdyf())
325            .field("pllrdyf", &self.pllrdyf())
326            .field("pll2rdyf", &self.pll2rdyf())
327            .field("pll3rdyf", &self.pll3rdyf())
328            .field("cssf", &self.cssf())
329            .field("lsirdyie", &self.lsirdyie())
330            .field("lserdyie", &self.lserdyie())
331            .field("hsirdyie", &self.hsirdyie())
332            .field("hserdyie", &self.hserdyie())
333            .field("pllrdyie", &self.pllrdyie())
334            .field("pll2rdyie", &self.pll2rdyie())
335            .field("pll3rdyie", &self.pll3rdyie())
336            .finish()
337    }
338}
339impl W {
340    ///Bit 8 - LSI Ready Interrupt Enable
341    #[inline(always)]
342    pub fn lsirdyie(&mut self) -> LSIRDYIE_W<CIRrs> {
343        LSIRDYIE_W::new(self, 8)
344    }
345    ///Bit 9 - LSE Ready Interrupt Enable
346    #[inline(always)]
347    pub fn lserdyie(&mut self) -> LSERDYIE_W<CIRrs> {
348        LSERDYIE_W::new(self, 9)
349    }
350    ///Bit 10 - HSI Ready Interrupt Enable
351    #[inline(always)]
352    pub fn hsirdyie(&mut self) -> HSIRDYIE_W<CIRrs> {
353        HSIRDYIE_W::new(self, 10)
354    }
355    ///Bit 11 - HSE Ready Interrupt Enable
356    #[inline(always)]
357    pub fn hserdyie(&mut self) -> HSERDYIE_W<CIRrs> {
358        HSERDYIE_W::new(self, 11)
359    }
360    ///Bit 12 - PLL Ready Interrupt Enable
361    #[inline(always)]
362    pub fn pllrdyie(&mut self) -> PLLRDYIE_W<CIRrs> {
363        PLLRDYIE_W::new(self, 12)
364    }
365    ///Bit 13 - PLL2 Ready Interrupt Enable
366    #[inline(always)]
367    pub fn pll2rdyie(&mut self) -> PLL2RDYIE_W<CIRrs> {
368        PLL2RDYIE_W::new(self, 13)
369    }
370    ///Bit 14 - PLL3 Ready Interrupt Enable
371    #[inline(always)]
372    pub fn pll3rdyie(&mut self) -> PLL3RDYIE_W<CIRrs> {
373        PLL3RDYIE_W::new(self, 14)
374    }
375    ///Bit 16 - LSI Ready Interrupt Clear
376    #[inline(always)]
377    pub fn lsirdyc(&mut self) -> LSIRDYC_W<CIRrs> {
378        LSIRDYC_W::new(self, 16)
379    }
380    ///Bit 17 - LSE Ready Interrupt Clear
381    #[inline(always)]
382    pub fn lserdyc(&mut self) -> LSERDYC_W<CIRrs> {
383        LSERDYC_W::new(self, 17)
384    }
385    ///Bit 18 - HSI Ready Interrupt Clear
386    #[inline(always)]
387    pub fn hsirdyc(&mut self) -> HSIRDYC_W<CIRrs> {
388        HSIRDYC_W::new(self, 18)
389    }
390    ///Bit 19 - HSE Ready Interrupt Clear
391    #[inline(always)]
392    pub fn hserdyc(&mut self) -> HSERDYC_W<CIRrs> {
393        HSERDYC_W::new(self, 19)
394    }
395    ///Bit 20 - PLL Ready Interrupt Clear
396    #[inline(always)]
397    pub fn pllrdyc(&mut self) -> PLLRDYC_W<CIRrs> {
398        PLLRDYC_W::new(self, 20)
399    }
400    ///Bit 21 - PLL2 Ready Interrupt Clear
401    #[inline(always)]
402    pub fn pll2rdyc(&mut self) -> PLL2RDYC_W<CIRrs> {
403        PLL2RDYC_W::new(self, 21)
404    }
405    ///Bit 22 - PLL3 Ready Interrupt Clear
406    #[inline(always)]
407    pub fn pll3rdyc(&mut self) -> PLL3RDYC_W<CIRrs> {
408        PLL3RDYC_W::new(self, 22)
409    }
410    ///Bit 23 - Clock security system interrupt clear
411    #[inline(always)]
412    pub fn cssc(&mut self) -> CSSC_W<CIRrs> {
413        CSSC_W::new(self, 23)
414    }
415}
416/**Clock interrupt register (RCC_CIR)
417
418You can [`read`](crate::Reg::read) this register and get [`cir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
419
420See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:CIR)*/
421pub struct CIRrs;
422impl crate::RegisterSpec for CIRrs {
423    type Ux = u32;
424}
425///`read()` method returns [`cir::R`](R) reader structure
426impl crate::Readable for CIRrs {}
427///`write(|w| ..)` method takes [`cir::W`](W) writer structure
428impl crate::Writable for CIRrs {
429    type Safety = crate::Unsafe;
430}
431///`reset()` method sets CIR to value 0
432impl crate::Resettable for CIRrs {}
stm32f1_staging/stm32f107/rcc/cir.rs

stm32f1_staging/stm32f107/rcc/
cir.rs
