stm32f1_staging/stm32f107/rcc/
apb2rstr.rs

1///Register `APB2RSTR` reader
2pub type R = crate::R<APB2RSTRrs>;
3///Register `APB2RSTR` writer
4pub type W = crate::W<APB2RSTRrs>;
5/**Alternate function I/O reset
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum AFIORST {
11    ///1: Reset the selected module
12    Reset = 1,
13}
14impl From<AFIORST> for bool {
15    #[inline(always)]
16    fn from(variant: AFIORST) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `AFIORST` reader - Alternate function I/O reset
21pub type AFIORST_R = crate::BitReader<AFIORST>;
22impl AFIORST_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> Option<AFIORST> {
26        match self.bits {
27            true => Some(AFIORST::Reset),
28            _ => None,
29        }
30    }
31    ///Reset the selected module
32    #[inline(always)]
33    pub fn is_reset(&self) -> bool {
34        *self == AFIORST::Reset
35    }
36}
37///Field `AFIORST` writer - Alternate function I/O reset
38pub type AFIORST_W<'a, REG> = crate::BitWriter<'a, REG, AFIORST>;
39impl<'a, REG> AFIORST_W<'a, REG>
40where
41    REG: crate::Writable + crate::RegisterSpec,
42{
43    ///Reset the selected module
44    #[inline(always)]
45    pub fn reset(self) -> &'a mut crate::W<REG> {
46        self.variant(AFIORST::Reset)
47    }
48}
49///Field `IOPARST` reader - IO port A reset
50pub use AFIORST_R as IOPARST_R;
51///Field `IOPBRST` reader - IO port B reset
52pub use AFIORST_R as IOPBRST_R;
53///Field `IOPCRST` reader - IO port C reset
54pub use AFIORST_R as IOPCRST_R;
55///Field `IOPDRST` reader - IO port D reset
56pub use AFIORST_R as IOPDRST_R;
57///Field `IOPERST` reader - IO port E reset
58pub use AFIORST_R as IOPERST_R;
59///Field `ADC1RST` reader - ADC 1 interface reset
60pub use AFIORST_R as ADC1RST_R;
61///Field `ADC2RST` reader - ADC 2 interface reset
62pub use AFIORST_R as ADC2RST_R;
63///Field `TIM1RST` reader - TIM1 timer reset
64pub use AFIORST_R as TIM1RST_R;
65///Field `SPI1RST` reader - SPI 1 reset
66pub use AFIORST_R as SPI1RST_R;
67///Field `USART1RST` reader - USART1 reset
68pub use AFIORST_R as USART1RST_R;
69///Field `IOPARST` writer - IO port A reset
70pub use AFIORST_W as IOPARST_W;
71///Field `IOPBRST` writer - IO port B reset
72pub use AFIORST_W as IOPBRST_W;
73///Field `IOPCRST` writer - IO port C reset
74pub use AFIORST_W as IOPCRST_W;
75///Field `IOPDRST` writer - IO port D reset
76pub use AFIORST_W as IOPDRST_W;
77///Field `IOPERST` writer - IO port E reset
78pub use AFIORST_W as IOPERST_W;
79///Field `ADC1RST` writer - ADC 1 interface reset
80pub use AFIORST_W as ADC1RST_W;
81///Field `ADC2RST` writer - ADC 2 interface reset
82pub use AFIORST_W as ADC2RST_W;
83///Field `TIM1RST` writer - TIM1 timer reset
84pub use AFIORST_W as TIM1RST_W;
85///Field `SPI1RST` writer - SPI 1 reset
86pub use AFIORST_W as SPI1RST_W;
87///Field `USART1RST` writer - USART1 reset
88pub use AFIORST_W as USART1RST_W;
89impl R {
90    ///Bit 0 - Alternate function I/O reset
91    #[inline(always)]
92    pub fn afiorst(&self) -> AFIORST_R {
93        AFIORST_R::new((self.bits & 1) != 0)
94    }
95    ///Bit 2 - IO port A reset
96    #[inline(always)]
97    pub fn ioparst(&self) -> IOPARST_R {
98        IOPARST_R::new(((self.bits >> 2) & 1) != 0)
99    }
100    ///Bit 3 - IO port B reset
101    #[inline(always)]
102    pub fn iopbrst(&self) -> IOPBRST_R {
103        IOPBRST_R::new(((self.bits >> 3) & 1) != 0)
104    }
105    ///Bit 4 - IO port C reset
106    #[inline(always)]
107    pub fn iopcrst(&self) -> IOPCRST_R {
108        IOPCRST_R::new(((self.bits >> 4) & 1) != 0)
109    }
110    ///Bit 5 - IO port D reset
111    #[inline(always)]
112    pub fn iopdrst(&self) -> IOPDRST_R {
113        IOPDRST_R::new(((self.bits >> 5) & 1) != 0)
114    }
115    ///Bit 6 - IO port E reset
116    #[inline(always)]
117    pub fn ioperst(&self) -> IOPERST_R {
118        IOPERST_R::new(((self.bits >> 6) & 1) != 0)
119    }
120    ///Bit 9 - ADC 1 interface reset
121    #[inline(always)]
122    pub fn adc1rst(&self) -> ADC1RST_R {
123        ADC1RST_R::new(((self.bits >> 9) & 1) != 0)
124    }
125    ///Bit 10 - ADC 2 interface reset
126    #[inline(always)]
127    pub fn adc2rst(&self) -> ADC2RST_R {
128        ADC2RST_R::new(((self.bits >> 10) & 1) != 0)
129    }
130    ///Bit 11 - TIM1 timer reset
131    #[inline(always)]
132    pub fn tim1rst(&self) -> TIM1RST_R {
133        TIM1RST_R::new(((self.bits >> 11) & 1) != 0)
134    }
135    ///Bit 12 - SPI 1 reset
136    #[inline(always)]
137    pub fn spi1rst(&self) -> SPI1RST_R {
138        SPI1RST_R::new(((self.bits >> 12) & 1) != 0)
139    }
140    ///Bit 14 - USART1 reset
141    #[inline(always)]
142    pub fn usart1rst(&self) -> USART1RST_R {
143        USART1RST_R::new(((self.bits >> 14) & 1) != 0)
144    }
145}
146impl core::fmt::Debug for R {
147    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
148        f.debug_struct("APB2RSTR")
149            .field("afiorst", &self.afiorst())
150            .field("ioparst", &self.ioparst())
151            .field("iopbrst", &self.iopbrst())
152            .field("iopcrst", &self.iopcrst())
153            .field("iopdrst", &self.iopdrst())
154            .field("ioperst", &self.ioperst())
155            .field("adc1rst", &self.adc1rst())
156            .field("adc2rst", &self.adc2rst())
157            .field("tim1rst", &self.tim1rst())
158            .field("spi1rst", &self.spi1rst())
159            .field("usart1rst", &self.usart1rst())
160            .finish()
161    }
162}
163impl W {
164    ///Bit 0 - Alternate function I/O reset
165    #[inline(always)]
166    pub fn afiorst(&mut self) -> AFIORST_W<APB2RSTRrs> {
167        AFIORST_W::new(self, 0)
168    }
169    ///Bit 2 - IO port A reset
170    #[inline(always)]
171    pub fn ioparst(&mut self) -> IOPARST_W<APB2RSTRrs> {
172        IOPARST_W::new(self, 2)
173    }
174    ///Bit 3 - IO port B reset
175    #[inline(always)]
176    pub fn iopbrst(&mut self) -> IOPBRST_W<APB2RSTRrs> {
177        IOPBRST_W::new(self, 3)
178    }
179    ///Bit 4 - IO port C reset
180    #[inline(always)]
181    pub fn iopcrst(&mut self) -> IOPCRST_W<APB2RSTRrs> {
182        IOPCRST_W::new(self, 4)
183    }
184    ///Bit 5 - IO port D reset
185    #[inline(always)]
186    pub fn iopdrst(&mut self) -> IOPDRST_W<APB2RSTRrs> {
187        IOPDRST_W::new(self, 5)
188    }
189    ///Bit 6 - IO port E reset
190    #[inline(always)]
191    pub fn ioperst(&mut self) -> IOPERST_W<APB2RSTRrs> {
192        IOPERST_W::new(self, 6)
193    }
194    ///Bit 9 - ADC 1 interface reset
195    #[inline(always)]
196    pub fn adc1rst(&mut self) -> ADC1RST_W<APB2RSTRrs> {
197        ADC1RST_W::new(self, 9)
198    }
199    ///Bit 10 - ADC 2 interface reset
200    #[inline(always)]
201    pub fn adc2rst(&mut self) -> ADC2RST_W<APB2RSTRrs> {
202        ADC2RST_W::new(self, 10)
203    }
204    ///Bit 11 - TIM1 timer reset
205    #[inline(always)]
206    pub fn tim1rst(&mut self) -> TIM1RST_W<APB2RSTRrs> {
207        TIM1RST_W::new(self, 11)
208    }
209    ///Bit 12 - SPI 1 reset
210    #[inline(always)]
211    pub fn spi1rst(&mut self) -> SPI1RST_W<APB2RSTRrs> {
212        SPI1RST_W::new(self, 12)
213    }
214    ///Bit 14 - USART1 reset
215    #[inline(always)]
216    pub fn usart1rst(&mut self) -> USART1RST_W<APB2RSTRrs> {
217        USART1RST_W::new(self, 14)
218    }
219}
220/**APB2 peripheral reset register (RCC_APB2RSTR)
221
222You can [`read`](crate::Reg::read) this register and get [`apb2rstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2rstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
223
224See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:APB2RSTR)*/
225pub struct APB2RSTRrs;
226impl crate::RegisterSpec for APB2RSTRrs {
227    type Ux = u32;
228}
229///`read()` method returns [`apb2rstr::R`](R) reader structure
230impl crate::Readable for APB2RSTRrs {}
231///`write(|w| ..)` method takes [`apb2rstr::W`](W) writer structure
232impl crate::Writable for APB2RSTRrs {
233    type Safety = crate::Unsafe;
234}
235///`reset()` method sets APB2RSTR to value 0
236impl crate::Resettable for APB2RSTRrs {}
stm32f1_staging/stm32f107/rcc/apb2rstr.rs

stm32f1_staging/stm32f107/rcc/
apb2rstr.rs
