stm32f1_staging/stm32f107/rcc/
apb2enr.rs

1///Register `APB2ENR` reader
2pub type R = crate::R<APB2ENRrs>;
3///Register `APB2ENR` writer
4pub type W = crate::W<APB2ENRrs>;
5/**Alternate function I/O clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum AFIOEN {
11    ///0: The selected clock is disabled
12    Disabled = 0,
13    ///1: The selected clock is enabled
14    Enabled = 1,
15}
16impl From<AFIOEN> for bool {
17    #[inline(always)]
18    fn from(variant: AFIOEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `AFIOEN` reader - Alternate function I/O clock enable
23pub type AFIOEN_R = crate::BitReader<AFIOEN>;
24impl AFIOEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> AFIOEN {
28        match self.bits {
29            false => AFIOEN::Disabled,
30            true => AFIOEN::Enabled,
31        }
32    }
33    ///The selected clock is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == AFIOEN::Disabled
37    }
38    ///The selected clock is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == AFIOEN::Enabled
42    }
43}
44///Field `AFIOEN` writer - Alternate function I/O clock enable
45pub type AFIOEN_W<'a, REG> = crate::BitWriter<'a, REG, AFIOEN>;
46impl<'a, REG> AFIOEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The selected clock is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(AFIOEN::Disabled)
54    }
55    ///The selected clock is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(AFIOEN::Enabled)
59    }
60}
61///Field `IOPAEN` reader - I/O port A clock enable
62pub use AFIOEN_R as IOPAEN_R;
63///Field `IOPBEN` reader - I/O port B clock enable
64pub use AFIOEN_R as IOPBEN_R;
65///Field `IOPCEN` reader - I/O port C clock enable
66pub use AFIOEN_R as IOPCEN_R;
67///Field `IOPDEN` reader - I/O port D clock enable
68pub use AFIOEN_R as IOPDEN_R;
69///Field `IOPEEN` reader - I/O port E clock enable
70pub use AFIOEN_R as IOPEEN_R;
71///Field `ADC1EN` reader - ADC 1 interface clock enable
72pub use AFIOEN_R as ADC1EN_R;
73///Field `ADC2EN` reader - ADC 2 interface clock enable
74pub use AFIOEN_R as ADC2EN_R;
75///Field `TIM1EN` reader - TIM1 Timer clock enable
76pub use AFIOEN_R as TIM1EN_R;
77///Field `SPI1EN` reader - SPI 1 clock enable
78pub use AFIOEN_R as SPI1EN_R;
79///Field `USART1EN` reader - USART1 clock enable
80pub use AFIOEN_R as USART1EN_R;
81///Field `IOPAEN` writer - I/O port A clock enable
82pub use AFIOEN_W as IOPAEN_W;
83///Field `IOPBEN` writer - I/O port B clock enable
84pub use AFIOEN_W as IOPBEN_W;
85///Field `IOPCEN` writer - I/O port C clock enable
86pub use AFIOEN_W as IOPCEN_W;
87///Field `IOPDEN` writer - I/O port D clock enable
88pub use AFIOEN_W as IOPDEN_W;
89///Field `IOPEEN` writer - I/O port E clock enable
90pub use AFIOEN_W as IOPEEN_W;
91///Field `ADC1EN` writer - ADC 1 interface clock enable
92pub use AFIOEN_W as ADC1EN_W;
93///Field `ADC2EN` writer - ADC 2 interface clock enable
94pub use AFIOEN_W as ADC2EN_W;
95///Field `TIM1EN` writer - TIM1 Timer clock enable
96pub use AFIOEN_W as TIM1EN_W;
97///Field `SPI1EN` writer - SPI 1 clock enable
98pub use AFIOEN_W as SPI1EN_W;
99///Field `USART1EN` writer - USART1 clock enable
100pub use AFIOEN_W as USART1EN_W;
101impl R {
102    ///Bit 0 - Alternate function I/O clock enable
103    #[inline(always)]
104    pub fn afioen(&self) -> AFIOEN_R {
105        AFIOEN_R::new((self.bits & 1) != 0)
106    }
107    ///Bit 2 - I/O port A clock enable
108    #[inline(always)]
109    pub fn iopaen(&self) -> IOPAEN_R {
110        IOPAEN_R::new(((self.bits >> 2) & 1) != 0)
111    }
112    ///Bit 3 - I/O port B clock enable
113    #[inline(always)]
114    pub fn iopben(&self) -> IOPBEN_R {
115        IOPBEN_R::new(((self.bits >> 3) & 1) != 0)
116    }
117    ///Bit 4 - I/O port C clock enable
118    #[inline(always)]
119    pub fn iopcen(&self) -> IOPCEN_R {
120        IOPCEN_R::new(((self.bits >> 4) & 1) != 0)
121    }
122    ///Bit 5 - I/O port D clock enable
123    #[inline(always)]
124    pub fn iopden(&self) -> IOPDEN_R {
125        IOPDEN_R::new(((self.bits >> 5) & 1) != 0)
126    }
127    ///Bit 6 - I/O port E clock enable
128    #[inline(always)]
129    pub fn iopeen(&self) -> IOPEEN_R {
130        IOPEEN_R::new(((self.bits >> 6) & 1) != 0)
131    }
132    ///Bit 9 - ADC 1 interface clock enable
133    #[inline(always)]
134    pub fn adc1en(&self) -> ADC1EN_R {
135        ADC1EN_R::new(((self.bits >> 9) & 1) != 0)
136    }
137    ///Bit 10 - ADC 2 interface clock enable
138    #[inline(always)]
139    pub fn adc2en(&self) -> ADC2EN_R {
140        ADC2EN_R::new(((self.bits >> 10) & 1) != 0)
141    }
142    ///Bit 11 - TIM1 Timer clock enable
143    #[inline(always)]
144    pub fn tim1en(&self) -> TIM1EN_R {
145        TIM1EN_R::new(((self.bits >> 11) & 1) != 0)
146    }
147    ///Bit 12 - SPI 1 clock enable
148    #[inline(always)]
149    pub fn spi1en(&self) -> SPI1EN_R {
150        SPI1EN_R::new(((self.bits >> 12) & 1) != 0)
151    }
152    ///Bit 14 - USART1 clock enable
153    #[inline(always)]
154    pub fn usart1en(&self) -> USART1EN_R {
155        USART1EN_R::new(((self.bits >> 14) & 1) != 0)
156    }
157}
158impl core::fmt::Debug for R {
159    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
160        f.debug_struct("APB2ENR")
161            .field("afioen", &self.afioen())
162            .field("iopaen", &self.iopaen())
163            .field("iopben", &self.iopben())
164            .field("iopcen", &self.iopcen())
165            .field("iopden", &self.iopden())
166            .field("iopeen", &self.iopeen())
167            .field("adc1en", &self.adc1en())
168            .field("adc2en", &self.adc2en())
169            .field("tim1en", &self.tim1en())
170            .field("spi1en", &self.spi1en())
171            .field("usart1en", &self.usart1en())
172            .finish()
173    }
174}
175impl W {
176    ///Bit 0 - Alternate function I/O clock enable
177    #[inline(always)]
178    pub fn afioen(&mut self) -> AFIOEN_W<APB2ENRrs> {
179        AFIOEN_W::new(self, 0)
180    }
181    ///Bit 2 - I/O port A clock enable
182    #[inline(always)]
183    pub fn iopaen(&mut self) -> IOPAEN_W<APB2ENRrs> {
184        IOPAEN_W::new(self, 2)
185    }
186    ///Bit 3 - I/O port B clock enable
187    #[inline(always)]
188    pub fn iopben(&mut self) -> IOPBEN_W<APB2ENRrs> {
189        IOPBEN_W::new(self, 3)
190    }
191    ///Bit 4 - I/O port C clock enable
192    #[inline(always)]
193    pub fn iopcen(&mut self) -> IOPCEN_W<APB2ENRrs> {
194        IOPCEN_W::new(self, 4)
195    }
196    ///Bit 5 - I/O port D clock enable
197    #[inline(always)]
198    pub fn iopden(&mut self) -> IOPDEN_W<APB2ENRrs> {
199        IOPDEN_W::new(self, 5)
200    }
201    ///Bit 6 - I/O port E clock enable
202    #[inline(always)]
203    pub fn iopeen(&mut self) -> IOPEEN_W<APB2ENRrs> {
204        IOPEEN_W::new(self, 6)
205    }
206    ///Bit 9 - ADC 1 interface clock enable
207    #[inline(always)]
208    pub fn adc1en(&mut self) -> ADC1EN_W<APB2ENRrs> {
209        ADC1EN_W::new(self, 9)
210    }
211    ///Bit 10 - ADC 2 interface clock enable
212    #[inline(always)]
213    pub fn adc2en(&mut self) -> ADC2EN_W<APB2ENRrs> {
214        ADC2EN_W::new(self, 10)
215    }
216    ///Bit 11 - TIM1 Timer clock enable
217    #[inline(always)]
218    pub fn tim1en(&mut self) -> TIM1EN_W<APB2ENRrs> {
219        TIM1EN_W::new(self, 11)
220    }
221    ///Bit 12 - SPI 1 clock enable
222    #[inline(always)]
223    pub fn spi1en(&mut self) -> SPI1EN_W<APB2ENRrs> {
224        SPI1EN_W::new(self, 12)
225    }
226    ///Bit 14 - USART1 clock enable
227    #[inline(always)]
228    pub fn usart1en(&mut self) -> USART1EN_W<APB2ENRrs> {
229        USART1EN_W::new(self, 14)
230    }
231}
232/**APB2 peripheral clock enable register (RCC_APB2ENR)
233
234You can [`read`](crate::Reg::read) this register and get [`apb2enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
235
236See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:APB2ENR)*/
237pub struct APB2ENRrs;
238impl crate::RegisterSpec for APB2ENRrs {
239    type Ux = u32;
240}
241///`read()` method returns [`apb2enr::R`](R) reader structure
242impl crate::Readable for APB2ENRrs {}
243///`write(|w| ..)` method takes [`apb2enr::W`](W) writer structure
244impl crate::Writable for APB2ENRrs {
245    type Safety = crate::Unsafe;
246}
247///`reset()` method sets APB2ENR to value 0
248impl crate::Resettable for APB2ENRrs {}
stm32f1_staging/stm32f107/rcc/apb2enr.rs

stm32f1_staging/stm32f107/rcc/
apb2enr.rs
