stm32f1_staging/stm32f107/rcc/
apb1enr.rs

1///Register `APB1ENR` reader
2pub type R = crate::R<APB1ENRrs>;
3///Register `APB1ENR` writer
4pub type W = crate::W<APB1ENRrs>;
5/**Timer 2 clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum TIM2EN {
11    ///0: The selected clock is disabled
12    Disabled = 0,
13    ///1: The selected clock is enabled
14    Enabled = 1,
15}
16impl From<TIM2EN> for bool {
17    #[inline(always)]
18    fn from(variant: TIM2EN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `TIM2EN` reader - Timer 2 clock enable
23pub type TIM2EN_R = crate::BitReader<TIM2EN>;
24impl TIM2EN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> TIM2EN {
28        match self.bits {
29            false => TIM2EN::Disabled,
30            true => TIM2EN::Enabled,
31        }
32    }
33    ///The selected clock is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == TIM2EN::Disabled
37    }
38    ///The selected clock is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == TIM2EN::Enabled
42    }
43}
44///Field `TIM2EN` writer - Timer 2 clock enable
45pub type TIM2EN_W<'a, REG> = crate::BitWriter<'a, REG, TIM2EN>;
46impl<'a, REG> TIM2EN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The selected clock is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(TIM2EN::Disabled)
54    }
55    ///The selected clock is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(TIM2EN::Enabled)
59    }
60}
61///Field `TIM3EN` reader - Timer 3 clock enable
62pub use TIM2EN_R as TIM3EN_R;
63///Field `TIM4EN` reader - Timer 4 clock enable
64pub use TIM2EN_R as TIM4EN_R;
65///Field `TIM5EN` reader - Timer 5 clock enable
66pub use TIM2EN_R as TIM5EN_R;
67///Field `TIM6EN` reader - Timer 6 clock enable
68pub use TIM2EN_R as TIM6EN_R;
69///Field `TIM7EN` reader - Timer 7 clock enable
70pub use TIM2EN_R as TIM7EN_R;
71///Field `WWDGEN` reader - Window watchdog clock enable
72pub use TIM2EN_R as WWDGEN_R;
73///Field `SPI2EN` reader - SPI 2 clock enable
74pub use TIM2EN_R as SPI2EN_R;
75///Field `SPI3EN` reader - SPI 3 clock enable
76pub use TIM2EN_R as SPI3EN_R;
77///Field `USART2EN` reader - USART 2 clock enable
78pub use TIM2EN_R as USART2EN_R;
79///Field `USART3EN` reader - USART 3 clock enable
80pub use TIM2EN_R as USART3EN_R;
81///Field `UART4EN` reader - UART 4 clock enable
82pub use TIM2EN_R as UART4EN_R;
83///Field `UART5EN` reader - UART 5 clock enable
84pub use TIM2EN_R as UART5EN_R;
85///Field `I2C1EN` reader - I2C 1 clock enable
86pub use TIM2EN_R as I2C1EN_R;
87///Field `I2C2EN` reader - I2C 2 clock enable
88pub use TIM2EN_R as I2C2EN_R;
89///Field `CAN1EN` reader - CAN1 clock enable
90pub use TIM2EN_R as CAN1EN_R;
91///Field `CAN2EN` reader - CAN2 clock enable
92pub use TIM2EN_R as CAN2EN_R;
93///Field `BKPEN` reader - Backup interface clock enable
94pub use TIM2EN_R as BKPEN_R;
95///Field `PWREN` reader - Power interface clock enable
96pub use TIM2EN_R as PWREN_R;
97///Field `DACEN` reader - DAC interface clock enable
98pub use TIM2EN_R as DACEN_R;
99///Field `TIM3EN` writer - Timer 3 clock enable
100pub use TIM2EN_W as TIM3EN_W;
101///Field `TIM4EN` writer - Timer 4 clock enable
102pub use TIM2EN_W as TIM4EN_W;
103///Field `TIM5EN` writer - Timer 5 clock enable
104pub use TIM2EN_W as TIM5EN_W;
105///Field `TIM6EN` writer - Timer 6 clock enable
106pub use TIM2EN_W as TIM6EN_W;
107///Field `TIM7EN` writer - Timer 7 clock enable
108pub use TIM2EN_W as TIM7EN_W;
109///Field `WWDGEN` writer - Window watchdog clock enable
110pub use TIM2EN_W as WWDGEN_W;
111///Field `SPI2EN` writer - SPI 2 clock enable
112pub use TIM2EN_W as SPI2EN_W;
113///Field `SPI3EN` writer - SPI 3 clock enable
114pub use TIM2EN_W as SPI3EN_W;
115///Field `USART2EN` writer - USART 2 clock enable
116pub use TIM2EN_W as USART2EN_W;
117///Field `USART3EN` writer - USART 3 clock enable
118pub use TIM2EN_W as USART3EN_W;
119///Field `UART4EN` writer - UART 4 clock enable
120pub use TIM2EN_W as UART4EN_W;
121///Field `UART5EN` writer - UART 5 clock enable
122pub use TIM2EN_W as UART5EN_W;
123///Field `I2C1EN` writer - I2C 1 clock enable
124pub use TIM2EN_W as I2C1EN_W;
125///Field `I2C2EN` writer - I2C 2 clock enable
126pub use TIM2EN_W as I2C2EN_W;
127///Field `CAN1EN` writer - CAN1 clock enable
128pub use TIM2EN_W as CAN1EN_W;
129///Field `CAN2EN` writer - CAN2 clock enable
130pub use TIM2EN_W as CAN2EN_W;
131///Field `BKPEN` writer - Backup interface clock enable
132pub use TIM2EN_W as BKPEN_W;
133///Field `PWREN` writer - Power interface clock enable
134pub use TIM2EN_W as PWREN_W;
135///Field `DACEN` writer - DAC interface clock enable
136pub use TIM2EN_W as DACEN_W;
137impl R {
138    ///Bit 0 - Timer 2 clock enable
139    #[inline(always)]
140    pub fn tim2en(&self) -> TIM2EN_R {
141        TIM2EN_R::new((self.bits & 1) != 0)
142    }
143    ///Bit 1 - Timer 3 clock enable
144    #[inline(always)]
145    pub fn tim3en(&self) -> TIM3EN_R {
146        TIM3EN_R::new(((self.bits >> 1) & 1) != 0)
147    }
148    ///Bit 2 - Timer 4 clock enable
149    #[inline(always)]
150    pub fn tim4en(&self) -> TIM4EN_R {
151        TIM4EN_R::new(((self.bits >> 2) & 1) != 0)
152    }
153    ///Bit 3 - Timer 5 clock enable
154    #[inline(always)]
155    pub fn tim5en(&self) -> TIM5EN_R {
156        TIM5EN_R::new(((self.bits >> 3) & 1) != 0)
157    }
158    ///Bit 4 - Timer 6 clock enable
159    #[inline(always)]
160    pub fn tim6en(&self) -> TIM6EN_R {
161        TIM6EN_R::new(((self.bits >> 4) & 1) != 0)
162    }
163    ///Bit 5 - Timer 7 clock enable
164    #[inline(always)]
165    pub fn tim7en(&self) -> TIM7EN_R {
166        TIM7EN_R::new(((self.bits >> 5) & 1) != 0)
167    }
168    ///Bit 11 - Window watchdog clock enable
169    #[inline(always)]
170    pub fn wwdgen(&self) -> WWDGEN_R {
171        WWDGEN_R::new(((self.bits >> 11) & 1) != 0)
172    }
173    ///Bit 14 - SPI 2 clock enable
174    #[inline(always)]
175    pub fn spi2en(&self) -> SPI2EN_R {
176        SPI2EN_R::new(((self.bits >> 14) & 1) != 0)
177    }
178    ///Bit 15 - SPI 3 clock enable
179    #[inline(always)]
180    pub fn spi3en(&self) -> SPI3EN_R {
181        SPI3EN_R::new(((self.bits >> 15) & 1) != 0)
182    }
183    ///Bit 17 - USART 2 clock enable
184    #[inline(always)]
185    pub fn usart2en(&self) -> USART2EN_R {
186        USART2EN_R::new(((self.bits >> 17) & 1) != 0)
187    }
188    ///Bit 18 - USART 3 clock enable
189    #[inline(always)]
190    pub fn usart3en(&self) -> USART3EN_R {
191        USART3EN_R::new(((self.bits >> 18) & 1) != 0)
192    }
193    ///Bit 19 - UART 4 clock enable
194    #[inline(always)]
195    pub fn uart4en(&self) -> UART4EN_R {
196        UART4EN_R::new(((self.bits >> 19) & 1) != 0)
197    }
198    ///Bit 20 - UART 5 clock enable
199    #[inline(always)]
200    pub fn uart5en(&self) -> UART5EN_R {
201        UART5EN_R::new(((self.bits >> 20) & 1) != 0)
202    }
203    ///Bit 21 - I2C 1 clock enable
204    #[inline(always)]
205    pub fn i2c1en(&self) -> I2C1EN_R {
206        I2C1EN_R::new(((self.bits >> 21) & 1) != 0)
207    }
208    ///Bit 22 - I2C 2 clock enable
209    #[inline(always)]
210    pub fn i2c2en(&self) -> I2C2EN_R {
211        I2C2EN_R::new(((self.bits >> 22) & 1) != 0)
212    }
213    ///Bit 25 - CAN1 clock enable
214    #[inline(always)]
215    pub fn can1en(&self) -> CAN1EN_R {
216        CAN1EN_R::new(((self.bits >> 25) & 1) != 0)
217    }
218    ///Bit 26 - CAN2 clock enable
219    #[inline(always)]
220    pub fn can2en(&self) -> CAN2EN_R {
221        CAN2EN_R::new(((self.bits >> 26) & 1) != 0)
222    }
223    ///Bit 27 - Backup interface clock enable
224    #[inline(always)]
225    pub fn bkpen(&self) -> BKPEN_R {
226        BKPEN_R::new(((self.bits >> 27) & 1) != 0)
227    }
228    ///Bit 28 - Power interface clock enable
229    #[inline(always)]
230    pub fn pwren(&self) -> PWREN_R {
231        PWREN_R::new(((self.bits >> 28) & 1) != 0)
232    }
233    ///Bit 29 - DAC interface clock enable
234    #[inline(always)]
235    pub fn dacen(&self) -> DACEN_R {
236        DACEN_R::new(((self.bits >> 29) & 1) != 0)
237    }
238}
239impl core::fmt::Debug for R {
240    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
241        f.debug_struct("APB1ENR")
242            .field("tim2en", &self.tim2en())
243            .field("tim3en", &self.tim3en())
244            .field("tim4en", &self.tim4en())
245            .field("tim5en", &self.tim5en())
246            .field("tim6en", &self.tim6en())
247            .field("tim7en", &self.tim7en())
248            .field("wwdgen", &self.wwdgen())
249            .field("spi2en", &self.spi2en())
250            .field("spi3en", &self.spi3en())
251            .field("usart2en", &self.usart2en())
252            .field("usart3en", &self.usart3en())
253            .field("uart4en", &self.uart4en())
254            .field("uart5en", &self.uart5en())
255            .field("i2c1en", &self.i2c1en())
256            .field("i2c2en", &self.i2c2en())
257            .field("can1en", &self.can1en())
258            .field("can2en", &self.can2en())
259            .field("bkpen", &self.bkpen())
260            .field("pwren", &self.pwren())
261            .field("dacen", &self.dacen())
262            .finish()
263    }
264}
265impl W {
266    ///Bit 0 - Timer 2 clock enable
267    #[inline(always)]
268    pub fn tim2en(&mut self) -> TIM2EN_W<APB1ENRrs> {
269        TIM2EN_W::new(self, 0)
270    }
271    ///Bit 1 - Timer 3 clock enable
272    #[inline(always)]
273    pub fn tim3en(&mut self) -> TIM3EN_W<APB1ENRrs> {
274        TIM3EN_W::new(self, 1)
275    }
276    ///Bit 2 - Timer 4 clock enable
277    #[inline(always)]
278    pub fn tim4en(&mut self) -> TIM4EN_W<APB1ENRrs> {
279        TIM4EN_W::new(self, 2)
280    }
281    ///Bit 3 - Timer 5 clock enable
282    #[inline(always)]
283    pub fn tim5en(&mut self) -> TIM5EN_W<APB1ENRrs> {
284        TIM5EN_W::new(self, 3)
285    }
286    ///Bit 4 - Timer 6 clock enable
287    #[inline(always)]
288    pub fn tim6en(&mut self) -> TIM6EN_W<APB1ENRrs> {
289        TIM6EN_W::new(self, 4)
290    }
291    ///Bit 5 - Timer 7 clock enable
292    #[inline(always)]
293    pub fn tim7en(&mut self) -> TIM7EN_W<APB1ENRrs> {
294        TIM7EN_W::new(self, 5)
295    }
296    ///Bit 11 - Window watchdog clock enable
297    #[inline(always)]
298    pub fn wwdgen(&mut self) -> WWDGEN_W<APB1ENRrs> {
299        WWDGEN_W::new(self, 11)
300    }
301    ///Bit 14 - SPI 2 clock enable
302    #[inline(always)]
303    pub fn spi2en(&mut self) -> SPI2EN_W<APB1ENRrs> {
304        SPI2EN_W::new(self, 14)
305    }
306    ///Bit 15 - SPI 3 clock enable
307    #[inline(always)]
308    pub fn spi3en(&mut self) -> SPI3EN_W<APB1ENRrs> {
309        SPI3EN_W::new(self, 15)
310    }
311    ///Bit 17 - USART 2 clock enable
312    #[inline(always)]
313    pub fn usart2en(&mut self) -> USART2EN_W<APB1ENRrs> {
314        USART2EN_W::new(self, 17)
315    }
316    ///Bit 18 - USART 3 clock enable
317    #[inline(always)]
318    pub fn usart3en(&mut self) -> USART3EN_W<APB1ENRrs> {
319        USART3EN_W::new(self, 18)
320    }
321    ///Bit 19 - UART 4 clock enable
322    #[inline(always)]
323    pub fn uart4en(&mut self) -> UART4EN_W<APB1ENRrs> {
324        UART4EN_W::new(self, 19)
325    }
326    ///Bit 20 - UART 5 clock enable
327    #[inline(always)]
328    pub fn uart5en(&mut self) -> UART5EN_W<APB1ENRrs> {
329        UART5EN_W::new(self, 20)
330    }
331    ///Bit 21 - I2C 1 clock enable
332    #[inline(always)]
333    pub fn i2c1en(&mut self) -> I2C1EN_W<APB1ENRrs> {
334        I2C1EN_W::new(self, 21)
335    }
336    ///Bit 22 - I2C 2 clock enable
337    #[inline(always)]
338    pub fn i2c2en(&mut self) -> I2C2EN_W<APB1ENRrs> {
339        I2C2EN_W::new(self, 22)
340    }
341    ///Bit 25 - CAN1 clock enable
342    #[inline(always)]
343    pub fn can1en(&mut self) -> CAN1EN_W<APB1ENRrs> {
344        CAN1EN_W::new(self, 25)
345    }
346    ///Bit 26 - CAN2 clock enable
347    #[inline(always)]
348    pub fn can2en(&mut self) -> CAN2EN_W<APB1ENRrs> {
349        CAN2EN_W::new(self, 26)
350    }
351    ///Bit 27 - Backup interface clock enable
352    #[inline(always)]
353    pub fn bkpen(&mut self) -> BKPEN_W<APB1ENRrs> {
354        BKPEN_W::new(self, 27)
355    }
356    ///Bit 28 - Power interface clock enable
357    #[inline(always)]
358    pub fn pwren(&mut self) -> PWREN_W<APB1ENRrs> {
359        PWREN_W::new(self, 28)
360    }
361    ///Bit 29 - DAC interface clock enable
362    #[inline(always)]
363    pub fn dacen(&mut self) -> DACEN_W<APB1ENRrs> {
364        DACEN_W::new(self, 29)
365    }
366}
367/**APB1 peripheral clock enable register (RCC_APB1ENR)
368
369You can [`read`](crate::Reg::read) this register and get [`apb1enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
370
371See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:APB1ENR)*/
372pub struct APB1ENRrs;
373impl crate::RegisterSpec for APB1ENRrs {
374    type Ux = u32;
375}
376///`read()` method returns [`apb1enr::R`](R) reader structure
377impl crate::Readable for APB1ENRrs {}
378///`write(|w| ..)` method takes [`apb1enr::W`](W) writer structure
379impl crate::Writable for APB1ENRrs {
380    type Safety = crate::Unsafe;
381}
382///`reset()` method sets APB1ENR to value 0
383impl crate::Resettable for APB1ENRrs {}
stm32f1_staging/stm32f107/rcc/apb1enr.rs

stm32f1_staging/stm32f107/rcc/
apb1enr.rs
