stm32f1_staging/stm32f107/rcc/
ahbrstr.rs

1///Register `AHBRSTR` reader
2pub type R = crate::R<AHBRSTRrs>;
3///Register `AHBRSTR` writer
4pub type W = crate::W<AHBRSTRrs>;
5/**USB OTG FS reset
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum OTGFSRST {
11    ///1: Reset the selected module
12    Reset = 1,
13}
14impl From<OTGFSRST> for bool {
15    #[inline(always)]
16    fn from(variant: OTGFSRST) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `OTGFSRST` reader - USB OTG FS reset
21pub type OTGFSRST_R = crate::BitReader<OTGFSRST>;
22impl OTGFSRST_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> Option<OTGFSRST> {
26        match self.bits {
27            true => Some(OTGFSRST::Reset),
28            _ => None,
29        }
30    }
31    ///Reset the selected module
32    #[inline(always)]
33    pub fn is_reset(&self) -> bool {
34        *self == OTGFSRST::Reset
35    }
36}
37///Field `OTGFSRST` writer - USB OTG FS reset
38pub type OTGFSRST_W<'a, REG> = crate::BitWriter<'a, REG, OTGFSRST>;
39impl<'a, REG> OTGFSRST_W<'a, REG>
40where
41    REG: crate::Writable + crate::RegisterSpec,
42{
43    ///Reset the selected module
44    #[inline(always)]
45    pub fn reset(self) -> &'a mut crate::W<REG> {
46        self.variant(OTGFSRST::Reset)
47    }
48}
49///Field `ETHMACRST` reader - Ethernet MAC reset
50pub use OTGFSRST_R as ETHMACRST_R;
51///Field `ETHMACRST` writer - Ethernet MAC reset
52pub use OTGFSRST_W as ETHMACRST_W;
53impl R {
54    ///Bit 12 - USB OTG FS reset
55    #[inline(always)]
56    pub fn otgfsrst(&self) -> OTGFSRST_R {
57        OTGFSRST_R::new(((self.bits >> 12) & 1) != 0)
58    }
59    ///Bit 14 - Ethernet MAC reset
60    #[inline(always)]
61    pub fn ethmacrst(&self) -> ETHMACRST_R {
62        ETHMACRST_R::new(((self.bits >> 14) & 1) != 0)
63    }
64}
65impl core::fmt::Debug for R {
66    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
67        f.debug_struct("AHBRSTR")
68            .field("otgfsrst", &self.otgfsrst())
69            .field("ethmacrst", &self.ethmacrst())
70            .finish()
71    }
72}
73impl W {
74    ///Bit 12 - USB OTG FS reset
75    #[inline(always)]
76    pub fn otgfsrst(&mut self) -> OTGFSRST_W<AHBRSTRrs> {
77        OTGFSRST_W::new(self, 12)
78    }
79    ///Bit 14 - Ethernet MAC reset
80    #[inline(always)]
81    pub fn ethmacrst(&mut self) -> ETHMACRST_W<AHBRSTRrs> {
82        ETHMACRST_W::new(self, 14)
83    }
84}
85/**AHB peripheral clock reset register (RCC_AHBRSTR)
86
87You can [`read`](crate::Reg::read) this register and get [`ahbrstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbrstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
88
89See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:AHBRSTR)*/
90pub struct AHBRSTRrs;
91impl crate::RegisterSpec for AHBRSTRrs {
92    type Ux = u32;
93}
94///`read()` method returns [`ahbrstr::R`](R) reader structure
95impl crate::Readable for AHBRSTRrs {}
96///`write(|w| ..)` method takes [`ahbrstr::W`](W) writer structure
97impl crate::Writable for AHBRSTRrs {
98    type Safety = crate::Unsafe;
99}
100///`reset()` method sets AHBRSTR to value 0
101impl crate::Resettable for AHBRSTRrs {}
stm32f1_staging/stm32f107/rcc/ahbrstr.rs

stm32f1_staging/stm32f107/rcc/
ahbrstr.rs
