stm32f1_staging/stm32f107/rcc/
ahbenr.rs

1///Register `AHBENR` reader
2pub type R = crate::R<AHBENRrs>;
3///Register `AHBENR` writer
4pub type W = crate::W<AHBENRrs>;
5/**DMA1 clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum DMA1EN {
11    ///0: The selected clock is disabled
12    Disabled = 0,
13    ///1: The selected clock is enabled
14    Enabled = 1,
15}
16impl From<DMA1EN> for bool {
17    #[inline(always)]
18    fn from(variant: DMA1EN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `DMA1EN` reader - DMA1 clock enable
23pub type DMA1EN_R = crate::BitReader<DMA1EN>;
24impl DMA1EN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> DMA1EN {
28        match self.bits {
29            false => DMA1EN::Disabled,
30            true => DMA1EN::Enabled,
31        }
32    }
33    ///The selected clock is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == DMA1EN::Disabled
37    }
38    ///The selected clock is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == DMA1EN::Enabled
42    }
43}
44///Field `DMA1EN` writer - DMA1 clock enable
45pub type DMA1EN_W<'a, REG> = crate::BitWriter<'a, REG, DMA1EN>;
46impl<'a, REG> DMA1EN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The selected clock is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(DMA1EN::Disabled)
54    }
55    ///The selected clock is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(DMA1EN::Enabled)
59    }
60}
61///Field `DMA2EN` reader - DMA2 clock enable
62pub use DMA1EN_R as DMA2EN_R;
63///Field `SRAMEN` reader - SRAM interface clock enable
64pub use DMA1EN_R as SRAMEN_R;
65///Field `FLITFEN` reader - FLITF clock enable
66pub use DMA1EN_R as FLITFEN_R;
67///Field `CRCEN` reader - CRC clock enable
68pub use DMA1EN_R as CRCEN_R;
69///Field `OTGFSEN` reader - USB OTG FS clock enable
70pub use DMA1EN_R as OTGFSEN_R;
71///Field `ETHMACEN` reader - Ethernet MAC clock enable
72pub use DMA1EN_R as ETHMACEN_R;
73///Field `ETHMACTXEN` reader - Ethernet MAC TX clock enable
74pub use DMA1EN_R as ETHMACTXEN_R;
75///Field `ETHMACRXEN` reader - Ethernet MAC RX clock enable
76pub use DMA1EN_R as ETHMACRXEN_R;
77///Field `DMA2EN` writer - DMA2 clock enable
78pub use DMA1EN_W as DMA2EN_W;
79///Field `SRAMEN` writer - SRAM interface clock enable
80pub use DMA1EN_W as SRAMEN_W;
81///Field `FLITFEN` writer - FLITF clock enable
82pub use DMA1EN_W as FLITFEN_W;
83///Field `CRCEN` writer - CRC clock enable
84pub use DMA1EN_W as CRCEN_W;
85///Field `OTGFSEN` writer - USB OTG FS clock enable
86pub use DMA1EN_W as OTGFSEN_W;
87///Field `ETHMACEN` writer - Ethernet MAC clock enable
88pub use DMA1EN_W as ETHMACEN_W;
89///Field `ETHMACTXEN` writer - Ethernet MAC TX clock enable
90pub use DMA1EN_W as ETHMACTXEN_W;
91///Field `ETHMACRXEN` writer - Ethernet MAC RX clock enable
92pub use DMA1EN_W as ETHMACRXEN_W;
93impl R {
94    ///Bit 0 - DMA1 clock enable
95    #[inline(always)]
96    pub fn dma1en(&self) -> DMA1EN_R {
97        DMA1EN_R::new((self.bits & 1) != 0)
98    }
99    ///Bit 1 - DMA2 clock enable
100    #[inline(always)]
101    pub fn dma2en(&self) -> DMA2EN_R {
102        DMA2EN_R::new(((self.bits >> 1) & 1) != 0)
103    }
104    ///Bit 2 - SRAM interface clock enable
105    #[inline(always)]
106    pub fn sramen(&self) -> SRAMEN_R {
107        SRAMEN_R::new(((self.bits >> 2) & 1) != 0)
108    }
109    ///Bit 4 - FLITF clock enable
110    #[inline(always)]
111    pub fn flitfen(&self) -> FLITFEN_R {
112        FLITFEN_R::new(((self.bits >> 4) & 1) != 0)
113    }
114    ///Bit 6 - CRC clock enable
115    #[inline(always)]
116    pub fn crcen(&self) -> CRCEN_R {
117        CRCEN_R::new(((self.bits >> 6) & 1) != 0)
118    }
119    ///Bit 12 - USB OTG FS clock enable
120    #[inline(always)]
121    pub fn otgfsen(&self) -> OTGFSEN_R {
122        OTGFSEN_R::new(((self.bits >> 12) & 1) != 0)
123    }
124    ///Bit 14 - Ethernet MAC clock enable
125    #[inline(always)]
126    pub fn ethmacen(&self) -> ETHMACEN_R {
127        ETHMACEN_R::new(((self.bits >> 14) & 1) != 0)
128    }
129    ///Bit 15 - Ethernet MAC TX clock enable
130    #[inline(always)]
131    pub fn ethmactxen(&self) -> ETHMACTXEN_R {
132        ETHMACTXEN_R::new(((self.bits >> 15) & 1) != 0)
133    }
134    ///Bit 16 - Ethernet MAC RX clock enable
135    #[inline(always)]
136    pub fn ethmacrxen(&self) -> ETHMACRXEN_R {
137        ETHMACRXEN_R::new(((self.bits >> 16) & 1) != 0)
138    }
139}
140impl core::fmt::Debug for R {
141    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
142        f.debug_struct("AHBENR")
143            .field("dma1en", &self.dma1en())
144            .field("dma2en", &self.dma2en())
145            .field("sramen", &self.sramen())
146            .field("flitfen", &self.flitfen())
147            .field("crcen", &self.crcen())
148            .field("otgfsen", &self.otgfsen())
149            .field("ethmacen", &self.ethmacen())
150            .field("ethmactxen", &self.ethmactxen())
151            .field("ethmacrxen", &self.ethmacrxen())
152            .finish()
153    }
154}
155impl W {
156    ///Bit 0 - DMA1 clock enable
157    #[inline(always)]
158    pub fn dma1en(&mut self) -> DMA1EN_W<AHBENRrs> {
159        DMA1EN_W::new(self, 0)
160    }
161    ///Bit 1 - DMA2 clock enable
162    #[inline(always)]
163    pub fn dma2en(&mut self) -> DMA2EN_W<AHBENRrs> {
164        DMA2EN_W::new(self, 1)
165    }
166    ///Bit 2 - SRAM interface clock enable
167    #[inline(always)]
168    pub fn sramen(&mut self) -> SRAMEN_W<AHBENRrs> {
169        SRAMEN_W::new(self, 2)
170    }
171    ///Bit 4 - FLITF clock enable
172    #[inline(always)]
173    pub fn flitfen(&mut self) -> FLITFEN_W<AHBENRrs> {
174        FLITFEN_W::new(self, 4)
175    }
176    ///Bit 6 - CRC clock enable
177    #[inline(always)]
178    pub fn crcen(&mut self) -> CRCEN_W<AHBENRrs> {
179        CRCEN_W::new(self, 6)
180    }
181    ///Bit 12 - USB OTG FS clock enable
182    #[inline(always)]
183    pub fn otgfsen(&mut self) -> OTGFSEN_W<AHBENRrs> {
184        OTGFSEN_W::new(self, 12)
185    }
186    ///Bit 14 - Ethernet MAC clock enable
187    #[inline(always)]
188    pub fn ethmacen(&mut self) -> ETHMACEN_W<AHBENRrs> {
189        ETHMACEN_W::new(self, 14)
190    }
191    ///Bit 15 - Ethernet MAC TX clock enable
192    #[inline(always)]
193    pub fn ethmactxen(&mut self) -> ETHMACTXEN_W<AHBENRrs> {
194        ETHMACTXEN_W::new(self, 15)
195    }
196    ///Bit 16 - Ethernet MAC RX clock enable
197    #[inline(always)]
198    pub fn ethmacrxen(&mut self) -> ETHMACRXEN_W<AHBENRrs> {
199        ETHMACRXEN_W::new(self, 16)
200    }
201}
202/**AHB Peripheral Clock enable register (RCC_AHBENR)
203
204You can [`read`](crate::Reg::read) this register and get [`ahbenr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbenr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
205
206See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:AHBENR)*/
207pub struct AHBENRrs;
208impl crate::RegisterSpec for AHBENRrs {
209    type Ux = u32;
210}
211///`read()` method returns [`ahbenr::R`](R) reader structure
212impl crate::Readable for AHBENRrs {}
213///`write(|w| ..)` method takes [`ahbenr::W`](W) writer structure
214impl crate::Writable for AHBENRrs {
215    type Safety = crate::Unsafe;
216}
217///`reset()` method sets AHBENR to value 0x14
218impl crate::Resettable for AHBENRrs {
219    const RESET_VALUE: u32 = 0x14;
220}
stm32f1_staging/stm32f107/rcc/ahbenr.rs

stm32f1_staging/stm32f107/rcc/
ahbenr.rs
