stm32f1_staging/stm32f107/i2c1/
ccr.rs

1///Register `CCR` reader
2pub type R = crate::R<CCRrs>;
3///Register `CCR` writer
4pub type W = crate::W<CCRrs>;
5///Field `CCR` reader - Clock control register in Fast/Standard mode (Master mode)
6pub type CCR_R = crate::FieldReader<u16>;
7///Field `CCR` writer - Clock control register in Fast/Standard mode (Master mode)
8pub type CCR_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9/**Fast mode duty cycle
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum DUTY {
15    ///0: Duty cycle t_low/t_high = 2/1
16    Duty2_1 = 0,
17    ///1: Duty cycle t_low/t_high = 16/9
18    Duty16_9 = 1,
19}
20impl From<DUTY> for bool {
21    #[inline(always)]
22    fn from(variant: DUTY) -> Self {
23        variant as u8 != 0
24    }
25}
26///Field `DUTY` reader - Fast mode duty cycle
27pub type DUTY_R = crate::BitReader<DUTY>;
28impl DUTY_R {
29    ///Get enumerated values variant
30    #[inline(always)]
31    pub const fn variant(&self) -> DUTY {
32        match self.bits {
33            false => DUTY::Duty2_1,
34            true => DUTY::Duty16_9,
35        }
36    }
37    ///Duty cycle t_low/t_high = 2/1
38    #[inline(always)]
39    pub fn is_duty2_1(&self) -> bool {
40        *self == DUTY::Duty2_1
41    }
42    ///Duty cycle t_low/t_high = 16/9
43    #[inline(always)]
44    pub fn is_duty16_9(&self) -> bool {
45        *self == DUTY::Duty16_9
46    }
47}
48///Field `DUTY` writer - Fast mode duty cycle
49pub type DUTY_W<'a, REG> = crate::BitWriter<'a, REG, DUTY>;
50impl<'a, REG> DUTY_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    ///Duty cycle t_low/t_high = 2/1
55    #[inline(always)]
56    pub fn duty2_1(self) -> &'a mut crate::W<REG> {
57        self.variant(DUTY::Duty2_1)
58    }
59    ///Duty cycle t_low/t_high = 16/9
60    #[inline(always)]
61    pub fn duty16_9(self) -> &'a mut crate::W<REG> {
62        self.variant(DUTY::Duty16_9)
63    }
64}
65/**I2C master mode selection
66
67Value on reset: 0*/
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum F_S {
71    ///0: Standard mode I2C
72    Standard = 0,
73    ///1: Fast mode I2C
74    Fast = 1,
75}
76impl From<F_S> for bool {
77    #[inline(always)]
78    fn from(variant: F_S) -> Self {
79        variant as u8 != 0
80    }
81}
82///Field `F_S` reader - I2C master mode selection
83pub type F_S_R = crate::BitReader<F_S>;
84impl F_S_R {
85    ///Get enumerated values variant
86    #[inline(always)]
87    pub const fn variant(&self) -> F_S {
88        match self.bits {
89            false => F_S::Standard,
90            true => F_S::Fast,
91        }
92    }
93    ///Standard mode I2C
94    #[inline(always)]
95    pub fn is_standard(&self) -> bool {
96        *self == F_S::Standard
97    }
98    ///Fast mode I2C
99    #[inline(always)]
100    pub fn is_fast(&self) -> bool {
101        *self == F_S::Fast
102    }
103}
104///Field `F_S` writer - I2C master mode selection
105pub type F_S_W<'a, REG> = crate::BitWriter<'a, REG, F_S>;
106impl<'a, REG> F_S_W<'a, REG>
107where
108    REG: crate::Writable + crate::RegisterSpec,
109{
110    ///Standard mode I2C
111    #[inline(always)]
112    pub fn standard(self) -> &'a mut crate::W<REG> {
113        self.variant(F_S::Standard)
114    }
115    ///Fast mode I2C
116    #[inline(always)]
117    pub fn fast(self) -> &'a mut crate::W<REG> {
118        self.variant(F_S::Fast)
119    }
120}
121impl R {
122    ///Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)
123    #[inline(always)]
124    pub fn ccr(&self) -> CCR_R {
125        CCR_R::new(self.bits & 0x0fff)
126    }
127    ///Bit 14 - Fast mode duty cycle
128    #[inline(always)]
129    pub fn duty(&self) -> DUTY_R {
130        DUTY_R::new(((self.bits >> 14) & 1) != 0)
131    }
132    ///Bit 15 - I2C master mode selection
133    #[inline(always)]
134    pub fn f_s(&self) -> F_S_R {
135        F_S_R::new(((self.bits >> 15) & 1) != 0)
136    }
137}
138impl core::fmt::Debug for R {
139    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
140        f.debug_struct("CCR")
141            .field("f_s", &self.f_s())
142            .field("duty", &self.duty())
143            .field("ccr", &self.ccr())
144            .finish()
145    }
146}
147impl W {
148    ///Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)
149    #[inline(always)]
150    pub fn ccr(&mut self) -> CCR_W<CCRrs> {
151        CCR_W::new(self, 0)
152    }
153    ///Bit 14 - Fast mode duty cycle
154    #[inline(always)]
155    pub fn duty(&mut self) -> DUTY_W<CCRrs> {
156        DUTY_W::new(self, 14)
157    }
158    ///Bit 15 - I2C master mode selection
159    #[inline(always)]
160    pub fn f_s(&mut self) -> F_S_W<CCRrs> {
161        F_S_W::new(self, 15)
162    }
163}
164/**Clock control register
165
166You can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#I2C1:CCR)*/
169pub struct CCRrs;
170impl crate::RegisterSpec for CCRrs {
171    type Ux = u16;
172}
173///`read()` method returns [`ccr::R`](R) reader structure
174impl crate::Readable for CCRrs {}
175///`write(|w| ..)` method takes [`ccr::W`](W) writer structure
176impl crate::Writable for CCRrs {
177    type Safety = crate::Unsafe;
178}
179///`reset()` method sets CCR to value 0
180impl crate::Resettable for CCRrs {}
stm32f1_staging/stm32f107/i2c1/ccr.rs

stm32f1_staging/stm32f107/i2c1/
ccr.rs
