stm32f1_staging/stm32f107/fsmc/
sr4.rs

1///Register `SR4` reader
2pub type R = crate::R<SR4rs>;
3///Register `SR4` writer
4pub type W = crate::W<SR4rs>;
5///Field `IRS` reader - IRS
6pub type IRS_R = crate::BitReader;
7///Field `IRS` writer - IRS
8pub type IRS_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `ILS` reader - ILS
10pub type ILS_R = crate::BitReader;
11///Field `ILS` writer - ILS
12pub type ILS_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `IFS` reader - IFS
14pub type IFS_R = crate::BitReader;
15///Field `IFS` writer - IFS
16pub type IFS_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `IREN` reader - IREN
18pub type IREN_R = crate::BitReader;
19///Field `IREN` writer - IREN
20pub type IREN_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `ILEN` reader - ILEN
22pub type ILEN_R = crate::BitReader;
23///Field `ILEN` writer - ILEN
24pub type ILEN_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `IFEN` reader - IFEN
26pub type IFEN_R = crate::BitReader;
27///Field `IFEN` writer - IFEN
28pub type IFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `FEMPT` reader - FEMPT
30pub type FEMPT_R = crate::BitReader;
31impl R {
32    ///Bit 0 - IRS
33    #[inline(always)]
34    pub fn irs(&self) -> IRS_R {
35        IRS_R::new((self.bits & 1) != 0)
36    }
37    ///Bit 1 - ILS
38    #[inline(always)]
39    pub fn ils(&self) -> ILS_R {
40        ILS_R::new(((self.bits >> 1) & 1) != 0)
41    }
42    ///Bit 2 - IFS
43    #[inline(always)]
44    pub fn ifs(&self) -> IFS_R {
45        IFS_R::new(((self.bits >> 2) & 1) != 0)
46    }
47    ///Bit 3 - IREN
48    #[inline(always)]
49    pub fn iren(&self) -> IREN_R {
50        IREN_R::new(((self.bits >> 3) & 1) != 0)
51    }
52    ///Bit 4 - ILEN
53    #[inline(always)]
54    pub fn ilen(&self) -> ILEN_R {
55        ILEN_R::new(((self.bits >> 4) & 1) != 0)
56    }
57    ///Bit 5 - IFEN
58    #[inline(always)]
59    pub fn ifen(&self) -> IFEN_R {
60        IFEN_R::new(((self.bits >> 5) & 1) != 0)
61    }
62    ///Bit 6 - FEMPT
63    #[inline(always)]
64    pub fn fempt(&self) -> FEMPT_R {
65        FEMPT_R::new(((self.bits >> 6) & 1) != 0)
66    }
67}
68impl core::fmt::Debug for R {
69    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
70        f.debug_struct("SR4")
71            .field("fempt", &self.fempt())
72            .field("ifen", &self.ifen())
73            .field("ilen", &self.ilen())
74            .field("iren", &self.iren())
75            .field("ifs", &self.ifs())
76            .field("ils", &self.ils())
77            .field("irs", &self.irs())
78            .finish()
79    }
80}
81impl W {
82    ///Bit 0 - IRS
83    #[inline(always)]
84    pub fn irs(&mut self) -> IRS_W<SR4rs> {
85        IRS_W::new(self, 0)
86    }
87    ///Bit 1 - ILS
88    #[inline(always)]
89    pub fn ils(&mut self) -> ILS_W<SR4rs> {
90        ILS_W::new(self, 1)
91    }
92    ///Bit 2 - IFS
93    #[inline(always)]
94    pub fn ifs(&mut self) -> IFS_W<SR4rs> {
95        IFS_W::new(self, 2)
96    }
97    ///Bit 3 - IREN
98    #[inline(always)]
99    pub fn iren(&mut self) -> IREN_W<SR4rs> {
100        IREN_W::new(self, 3)
101    }
102    ///Bit 4 - ILEN
103    #[inline(always)]
104    pub fn ilen(&mut self) -> ILEN_W<SR4rs> {
105        ILEN_W::new(self, 4)
106    }
107    ///Bit 5 - IFEN
108    #[inline(always)]
109    pub fn ifen(&mut self) -> IFEN_W<SR4rs> {
110        IFEN_W::new(self, 5)
111    }
112}
113/**FIFO status and interrupt register 4
114
115You can [`read`](crate::Reg::read) this register and get [`sr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
116
117See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#FSMC:SR4)*/
118pub struct SR4rs;
119impl crate::RegisterSpec for SR4rs {
120    type Ux = u32;
121}
122///`read()` method returns [`sr4::R`](R) reader structure
123impl crate::Readable for SR4rs {}
124///`write(|w| ..)` method takes [`sr4::W`](W) writer structure
125impl crate::Writable for SR4rs {
126    type Safety = crate::Unsafe;
127}
128///`reset()` method sets SR4 to value 0x40
129impl crate::Resettable for SR4rs {
130    const RESET_VALUE: u32 = 0x40;
131}
stm32f1_staging/stm32f107/fsmc/sr4.rs

stm32f1_staging/stm32f107/fsmc/
sr4.rs
