stm32f1_staging/stm32f107/fsmc/
bwtr1.rs

1///Register `BWTR1` reader
2pub type R = crate::R<BWTR1rs>;
3///Register `BWTR1` writer
4pub type W = crate::W<BWTR1rs>;
5///Field `ADDSET` reader - ADDSET
6pub type ADDSET_R = crate::FieldReader;
7///Field `ADDSET` writer - ADDSET
8pub type ADDSET_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9///Field `ADDHLD` reader - ADDHLD
10pub type ADDHLD_R = crate::FieldReader;
11///Field `ADDHLD` writer - ADDHLD
12pub type ADDHLD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13///Field `DATAST` reader - DATAST
14pub type DATAST_R = crate::FieldReader;
15///Field `DATAST` writer - DATAST
16pub type DATAST_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17///Field `CLKDIV` reader - CLKDIV
18pub type CLKDIV_R = crate::FieldReader;
19///Field `CLKDIV` writer - CLKDIV
20pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21///Field `DATLAT` reader - DATLAT
22pub type DATLAT_R = crate::FieldReader;
23///Field `DATLAT` writer - DATLAT
24pub type DATLAT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
25///Field `ACCMOD` reader - ACCMOD
26pub type ACCMOD_R = crate::FieldReader;
27///Field `ACCMOD` writer - ACCMOD
28pub type ACCMOD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29impl R {
30    ///Bits 0:3 - ADDSET
31    #[inline(always)]
32    pub fn addset(&self) -> ADDSET_R {
33        ADDSET_R::new((self.bits & 0x0f) as u8)
34    }
35    ///Bits 4:7 - ADDHLD
36    #[inline(always)]
37    pub fn addhld(&self) -> ADDHLD_R {
38        ADDHLD_R::new(((self.bits >> 4) & 0x0f) as u8)
39    }
40    ///Bits 8:15 - DATAST
41    #[inline(always)]
42    pub fn datast(&self) -> DATAST_R {
43        DATAST_R::new(((self.bits >> 8) & 0xff) as u8)
44    }
45    ///Bits 20:23 - CLKDIV
46    #[inline(always)]
47    pub fn clkdiv(&self) -> CLKDIV_R {
48        CLKDIV_R::new(((self.bits >> 20) & 0x0f) as u8)
49    }
50    ///Bits 24:27 - DATLAT
51    #[inline(always)]
52    pub fn datlat(&self) -> DATLAT_R {
53        DATLAT_R::new(((self.bits >> 24) & 0x0f) as u8)
54    }
55    ///Bits 28:29 - ACCMOD
56    #[inline(always)]
57    pub fn accmod(&self) -> ACCMOD_R {
58        ACCMOD_R::new(((self.bits >> 28) & 3) as u8)
59    }
60}
61impl core::fmt::Debug for R {
62    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
63        f.debug_struct("BWTR1")
64            .field("accmod", &self.accmod())
65            .field("datlat", &self.datlat())
66            .field("clkdiv", &self.clkdiv())
67            .field("datast", &self.datast())
68            .field("addhld", &self.addhld())
69            .field("addset", &self.addset())
70            .finish()
71    }
72}
73impl W {
74    ///Bits 0:3 - ADDSET
75    #[inline(always)]
76    pub fn addset(&mut self) -> ADDSET_W<BWTR1rs> {
77        ADDSET_W::new(self, 0)
78    }
79    ///Bits 4:7 - ADDHLD
80    #[inline(always)]
81    pub fn addhld(&mut self) -> ADDHLD_W<BWTR1rs> {
82        ADDHLD_W::new(self, 4)
83    }
84    ///Bits 8:15 - DATAST
85    #[inline(always)]
86    pub fn datast(&mut self) -> DATAST_W<BWTR1rs> {
87        DATAST_W::new(self, 8)
88    }
89    ///Bits 20:23 - CLKDIV
90    #[inline(always)]
91    pub fn clkdiv(&mut self) -> CLKDIV_W<BWTR1rs> {
92        CLKDIV_W::new(self, 20)
93    }
94    ///Bits 24:27 - DATLAT
95    #[inline(always)]
96    pub fn datlat(&mut self) -> DATLAT_W<BWTR1rs> {
97        DATLAT_W::new(self, 24)
98    }
99    ///Bits 28:29 - ACCMOD
100    #[inline(always)]
101    pub fn accmod(&mut self) -> ACCMOD_W<BWTR1rs> {
102        ACCMOD_W::new(self, 28)
103    }
104}
105/**SRAM/NOR-Flash write timing registers 1
106
107You can [`read`](crate::Reg::read) this register and get [`bwtr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bwtr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
108
109See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#FSMC:BWTR1)*/
110pub struct BWTR1rs;
111impl crate::RegisterSpec for BWTR1rs {
112    type Ux = u32;
113}
114///`read()` method returns [`bwtr1::R`](R) reader structure
115impl crate::Readable for BWTR1rs {}
116///`write(|w| ..)` method takes [`bwtr1::W`](W) writer structure
117impl crate::Writable for BWTR1rs {
118    type Safety = crate::Unsafe;
119}
120///`reset()` method sets BWTR1 to value 0x0fff_ffff
121impl crate::Resettable for BWTR1rs {
122    const RESET_VALUE: u32 = 0x0fff_ffff;
123}
stm32f1_staging/stm32f107/fsmc/bwtr1.rs

stm32f1_staging/stm32f107/fsmc/
bwtr1.rs
