stm32f1_staging/stm32f107/fsmc/
btr1.rs

1///Register `BTR1` reader
2pub type R = crate::R<BTR1rs>;
3///Register `BTR1` writer
4pub type W = crate::W<BTR1rs>;
5///Field `ADDSET` reader - ADDSET
6pub type ADDSET_R = crate::FieldReader;
7///Field `ADDSET` writer - ADDSET
8pub type ADDSET_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9///Field `ADDHLD` reader - ADDHLD
10pub type ADDHLD_R = crate::FieldReader;
11///Field `ADDHLD` writer - ADDHLD
12pub type ADDHLD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13///Field `DATAST` reader - DATAST
14pub type DATAST_R = crate::FieldReader;
15///Field `DATAST` writer - DATAST
16pub type DATAST_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17///Field `BUSTURN` reader - BUSTURN
18pub type BUSTURN_R = crate::FieldReader;
19///Field `BUSTURN` writer - BUSTURN
20pub type BUSTURN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21///Field `CLKDIV` reader - CLKDIV
22pub type CLKDIV_R = crate::FieldReader;
23///Field `CLKDIV` writer - CLKDIV
24pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
25///Field `DATLAT` reader - DATLAT
26pub type DATLAT_R = crate::FieldReader;
27///Field `DATLAT` writer - DATLAT
28pub type DATLAT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29///Field `ACCMOD` reader - ACCMOD
30pub type ACCMOD_R = crate::FieldReader;
31///Field `ACCMOD` writer - ACCMOD
32pub type ACCMOD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33impl R {
34    ///Bits 0:3 - ADDSET
35    #[inline(always)]
36    pub fn addset(&self) -> ADDSET_R {
37        ADDSET_R::new((self.bits & 0x0f) as u8)
38    }
39    ///Bits 4:7 - ADDHLD
40    #[inline(always)]
41    pub fn addhld(&self) -> ADDHLD_R {
42        ADDHLD_R::new(((self.bits >> 4) & 0x0f) as u8)
43    }
44    ///Bits 8:15 - DATAST
45    #[inline(always)]
46    pub fn datast(&self) -> DATAST_R {
47        DATAST_R::new(((self.bits >> 8) & 0xff) as u8)
48    }
49    ///Bits 16:19 - BUSTURN
50    #[inline(always)]
51    pub fn busturn(&self) -> BUSTURN_R {
52        BUSTURN_R::new(((self.bits >> 16) & 0x0f) as u8)
53    }
54    ///Bits 20:23 - CLKDIV
55    #[inline(always)]
56    pub fn clkdiv(&self) -> CLKDIV_R {
57        CLKDIV_R::new(((self.bits >> 20) & 0x0f) as u8)
58    }
59    ///Bits 24:27 - DATLAT
60    #[inline(always)]
61    pub fn datlat(&self) -> DATLAT_R {
62        DATLAT_R::new(((self.bits >> 24) & 0x0f) as u8)
63    }
64    ///Bits 28:29 - ACCMOD
65    #[inline(always)]
66    pub fn accmod(&self) -> ACCMOD_R {
67        ACCMOD_R::new(((self.bits >> 28) & 3) as u8)
68    }
69}
70impl core::fmt::Debug for R {
71    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
72        f.debug_struct("BTR1")
73            .field("accmod", &self.accmod())
74            .field("datlat", &self.datlat())
75            .field("clkdiv", &self.clkdiv())
76            .field("busturn", &self.busturn())
77            .field("datast", &self.datast())
78            .field("addhld", &self.addhld())
79            .field("addset", &self.addset())
80            .finish()
81    }
82}
83impl W {
84    ///Bits 0:3 - ADDSET
85    #[inline(always)]
86    pub fn addset(&mut self) -> ADDSET_W<BTR1rs> {
87        ADDSET_W::new(self, 0)
88    }
89    ///Bits 4:7 - ADDHLD
90    #[inline(always)]
91    pub fn addhld(&mut self) -> ADDHLD_W<BTR1rs> {
92        ADDHLD_W::new(self, 4)
93    }
94    ///Bits 8:15 - DATAST
95    #[inline(always)]
96    pub fn datast(&mut self) -> DATAST_W<BTR1rs> {
97        DATAST_W::new(self, 8)
98    }
99    ///Bits 16:19 - BUSTURN
100    #[inline(always)]
101    pub fn busturn(&mut self) -> BUSTURN_W<BTR1rs> {
102        BUSTURN_W::new(self, 16)
103    }
104    ///Bits 20:23 - CLKDIV
105    #[inline(always)]
106    pub fn clkdiv(&mut self) -> CLKDIV_W<BTR1rs> {
107        CLKDIV_W::new(self, 20)
108    }
109    ///Bits 24:27 - DATLAT
110    #[inline(always)]
111    pub fn datlat(&mut self) -> DATLAT_W<BTR1rs> {
112        DATLAT_W::new(self, 24)
113    }
114    ///Bits 28:29 - ACCMOD
115    #[inline(always)]
116    pub fn accmod(&mut self) -> ACCMOD_W<BTR1rs> {
117        ACCMOD_W::new(self, 28)
118    }
119}
120/**SRAM/NOR-Flash chip-select timing register 1
121
122You can [`read`](crate::Reg::read) this register and get [`btr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
123
124See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#FSMC:BTR1)*/
125pub struct BTR1rs;
126impl crate::RegisterSpec for BTR1rs {
127    type Ux = u32;
128}
129///`read()` method returns [`btr1::R`](R) reader structure
130impl crate::Readable for BTR1rs {}
131///`write(|w| ..)` method takes [`btr1::W`](W) writer structure
132impl crate::Writable for BTR1rs {
133    type Safety = crate::Unsafe;
134}
135///`reset()` method sets BTR1 to value 0xffff_ffff
136impl crate::Resettable for BTR1rs {
137    const RESET_VALUE: u32 = 0xffff_ffff;
138}
stm32f1_staging/stm32f107/fsmc/btr1.rs

stm32f1_staging/stm32f107/fsmc/
btr1.rs
