stm32f1_staging/stm32f107/fsmc/
bcr2.rs

1///Register `BCR2` reader
2pub type R = crate::R<BCR2rs>;
3///Register `BCR2` writer
4pub type W = crate::W<BCR2rs>;
5///Field `MBKEN` reader - MBKEN
6pub type MBKEN_R = crate::BitReader;
7///Field `MBKEN` writer - MBKEN
8pub type MBKEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `MUXEN` reader - MUXEN
10pub type MUXEN_R = crate::BitReader;
11///Field `MUXEN` writer - MUXEN
12pub type MUXEN_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `MTYP` reader - MTYP
14pub type MTYP_R = crate::FieldReader;
15///Field `MTYP` writer - MTYP
16pub type MTYP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17///Field `MWID` reader - MWID
18pub type MWID_R = crate::FieldReader;
19///Field `MWID` writer - MWID
20pub type MWID_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21///Field `FACCEN` reader - FACCEN
22pub type FACCEN_R = crate::BitReader;
23///Field `FACCEN` writer - FACCEN
24pub type FACCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `BURSTEN` reader - BURSTEN
26pub type BURSTEN_R = crate::BitReader;
27///Field `BURSTEN` writer - BURSTEN
28pub type BURSTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `WAITPOL` reader - WAITPOL
30pub type WAITPOL_R = crate::BitReader;
31///Field `WAITPOL` writer - WAITPOL
32pub type WAITPOL_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `WRAPMOD` reader - WRAPMOD
34pub type WRAPMOD_R = crate::BitReader;
35///Field `WRAPMOD` writer - WRAPMOD
36pub type WRAPMOD_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `WAITCFG` reader - WAITCFG
38pub type WAITCFG_R = crate::BitReader;
39///Field `WAITCFG` writer - WAITCFG
40pub type WAITCFG_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `WREN` reader - WREN
42pub type WREN_R = crate::BitReader;
43///Field `WREN` writer - WREN
44pub type WREN_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `WAITEN` reader - WAITEN
46pub type WAITEN_R = crate::BitReader;
47///Field `WAITEN` writer - WAITEN
48pub type WAITEN_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `EXTMOD` reader - EXTMOD
50pub type EXTMOD_R = crate::BitReader;
51///Field `EXTMOD` writer - EXTMOD
52pub type EXTMOD_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `ASYNCWAIT` reader - ASYNCWAIT
54pub type ASYNCWAIT_R = crate::BitReader;
55///Field `ASYNCWAIT` writer - ASYNCWAIT
56pub type ASYNCWAIT_W<'a, REG> = crate::BitWriter<'a, REG>;
57///Field `CBURSTRW` reader - CBURSTRW
58pub type CBURSTRW_R = crate::BitReader;
59///Field `CBURSTRW` writer - CBURSTRW
60pub type CBURSTRW_W<'a, REG> = crate::BitWriter<'a, REG>;
61impl R {
62    ///Bit 0 - MBKEN
63    #[inline(always)]
64    pub fn mbken(&self) -> MBKEN_R {
65        MBKEN_R::new((self.bits & 1) != 0)
66    }
67    ///Bit 1 - MUXEN
68    #[inline(always)]
69    pub fn muxen(&self) -> MUXEN_R {
70        MUXEN_R::new(((self.bits >> 1) & 1) != 0)
71    }
72    ///Bits 2:3 - MTYP
73    #[inline(always)]
74    pub fn mtyp(&self) -> MTYP_R {
75        MTYP_R::new(((self.bits >> 2) & 3) as u8)
76    }
77    ///Bits 4:5 - MWID
78    #[inline(always)]
79    pub fn mwid(&self) -> MWID_R {
80        MWID_R::new(((self.bits >> 4) & 3) as u8)
81    }
82    ///Bit 6 - FACCEN
83    #[inline(always)]
84    pub fn faccen(&self) -> FACCEN_R {
85        FACCEN_R::new(((self.bits >> 6) & 1) != 0)
86    }
87    ///Bit 8 - BURSTEN
88    #[inline(always)]
89    pub fn bursten(&self) -> BURSTEN_R {
90        BURSTEN_R::new(((self.bits >> 8) & 1) != 0)
91    }
92    ///Bit 9 - WAITPOL
93    #[inline(always)]
94    pub fn waitpol(&self) -> WAITPOL_R {
95        WAITPOL_R::new(((self.bits >> 9) & 1) != 0)
96    }
97    ///Bit 10 - WRAPMOD
98    #[inline(always)]
99    pub fn wrapmod(&self) -> WRAPMOD_R {
100        WRAPMOD_R::new(((self.bits >> 10) & 1) != 0)
101    }
102    ///Bit 11 - WAITCFG
103    #[inline(always)]
104    pub fn waitcfg(&self) -> WAITCFG_R {
105        WAITCFG_R::new(((self.bits >> 11) & 1) != 0)
106    }
107    ///Bit 12 - WREN
108    #[inline(always)]
109    pub fn wren(&self) -> WREN_R {
110        WREN_R::new(((self.bits >> 12) & 1) != 0)
111    }
112    ///Bit 13 - WAITEN
113    #[inline(always)]
114    pub fn waiten(&self) -> WAITEN_R {
115        WAITEN_R::new(((self.bits >> 13) & 1) != 0)
116    }
117    ///Bit 14 - EXTMOD
118    #[inline(always)]
119    pub fn extmod(&self) -> EXTMOD_R {
120        EXTMOD_R::new(((self.bits >> 14) & 1) != 0)
121    }
122    ///Bit 15 - ASYNCWAIT
123    #[inline(always)]
124    pub fn asyncwait(&self) -> ASYNCWAIT_R {
125        ASYNCWAIT_R::new(((self.bits >> 15) & 1) != 0)
126    }
127    ///Bit 19 - CBURSTRW
128    #[inline(always)]
129    pub fn cburstrw(&self) -> CBURSTRW_R {
130        CBURSTRW_R::new(((self.bits >> 19) & 1) != 0)
131    }
132}
133impl core::fmt::Debug for R {
134    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
135        f.debug_struct("BCR2")
136            .field("cburstrw", &self.cburstrw())
137            .field("asyncwait", &self.asyncwait())
138            .field("extmod", &self.extmod())
139            .field("waiten", &self.waiten())
140            .field("wren", &self.wren())
141            .field("waitcfg", &self.waitcfg())
142            .field("wrapmod", &self.wrapmod())
143            .field("waitpol", &self.waitpol())
144            .field("bursten", &self.bursten())
145            .field("faccen", &self.faccen())
146            .field("mwid", &self.mwid())
147            .field("mtyp", &self.mtyp())
148            .field("muxen", &self.muxen())
149            .field("mbken", &self.mbken())
150            .finish()
151    }
152}
153impl W {
154    ///Bit 0 - MBKEN
155    #[inline(always)]
156    pub fn mbken(&mut self) -> MBKEN_W<BCR2rs> {
157        MBKEN_W::new(self, 0)
158    }
159    ///Bit 1 - MUXEN
160    #[inline(always)]
161    pub fn muxen(&mut self) -> MUXEN_W<BCR2rs> {
162        MUXEN_W::new(self, 1)
163    }
164    ///Bits 2:3 - MTYP
165    #[inline(always)]
166    pub fn mtyp(&mut self) -> MTYP_W<BCR2rs> {
167        MTYP_W::new(self, 2)
168    }
169    ///Bits 4:5 - MWID
170    #[inline(always)]
171    pub fn mwid(&mut self) -> MWID_W<BCR2rs> {
172        MWID_W::new(self, 4)
173    }
174    ///Bit 6 - FACCEN
175    #[inline(always)]
176    pub fn faccen(&mut self) -> FACCEN_W<BCR2rs> {
177        FACCEN_W::new(self, 6)
178    }
179    ///Bit 8 - BURSTEN
180    #[inline(always)]
181    pub fn bursten(&mut self) -> BURSTEN_W<BCR2rs> {
182        BURSTEN_W::new(self, 8)
183    }
184    ///Bit 9 - WAITPOL
185    #[inline(always)]
186    pub fn waitpol(&mut self) -> WAITPOL_W<BCR2rs> {
187        WAITPOL_W::new(self, 9)
188    }
189    ///Bit 10 - WRAPMOD
190    #[inline(always)]
191    pub fn wrapmod(&mut self) -> WRAPMOD_W<BCR2rs> {
192        WRAPMOD_W::new(self, 10)
193    }
194    ///Bit 11 - WAITCFG
195    #[inline(always)]
196    pub fn waitcfg(&mut self) -> WAITCFG_W<BCR2rs> {
197        WAITCFG_W::new(self, 11)
198    }
199    ///Bit 12 - WREN
200    #[inline(always)]
201    pub fn wren(&mut self) -> WREN_W<BCR2rs> {
202        WREN_W::new(self, 12)
203    }
204    ///Bit 13 - WAITEN
205    #[inline(always)]
206    pub fn waiten(&mut self) -> WAITEN_W<BCR2rs> {
207        WAITEN_W::new(self, 13)
208    }
209    ///Bit 14 - EXTMOD
210    #[inline(always)]
211    pub fn extmod(&mut self) -> EXTMOD_W<BCR2rs> {
212        EXTMOD_W::new(self, 14)
213    }
214    ///Bit 15 - ASYNCWAIT
215    #[inline(always)]
216    pub fn asyncwait(&mut self) -> ASYNCWAIT_W<BCR2rs> {
217        ASYNCWAIT_W::new(self, 15)
218    }
219    ///Bit 19 - CBURSTRW
220    #[inline(always)]
221    pub fn cburstrw(&mut self) -> CBURSTRW_W<BCR2rs> {
222        CBURSTRW_W::new(self, 19)
223    }
224}
225/**SRAM/NOR-Flash chip-select control register 2
226
227You can [`read`](crate::Reg::read) this register and get [`bcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
228
229See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#FSMC:BCR2)*/
230pub struct BCR2rs;
231impl crate::RegisterSpec for BCR2rs {
232    type Ux = u32;
233}
234///`read()` method returns [`bcr2::R`](R) reader structure
235impl crate::Readable for BCR2rs {}
236///`write(|w| ..)` method takes [`bcr2::W`](W) writer structure
237impl crate::Writable for BCR2rs {
238    type Safety = crate::Unsafe;
239}
240///`reset()` method sets BCR2 to value 0x30d0
241impl crate::Resettable for BCR2rs {
242    const RESET_VALUE: u32 = 0x30d0;
243}
stm32f1_staging/stm32f107/fsmc/bcr2.rs

stm32f1_staging/stm32f107/fsmc/
bcr2.rs
