stm32f1_staging/stm32f107/fsmc/
bcr1.rs

1///Register `BCR1` reader
2pub type R = crate::R<BCR1rs>;
3///Register `BCR1` writer
4pub type W = crate::W<BCR1rs>;
5///Field `MBKEN` reader - MBKEN
6pub type MBKEN_R = crate::BitReader;
7///Field `MBKEN` writer - MBKEN
8pub type MBKEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `MUXEN` reader - MUXEN
10pub type MUXEN_R = crate::BitReader;
11///Field `MUXEN` writer - MUXEN
12pub type MUXEN_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `MTYP` reader - MTYP
14pub type MTYP_R = crate::FieldReader;
15///Field `MTYP` writer - MTYP
16pub type MTYP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17///Field `MWID` reader - MWID
18pub type MWID_R = crate::FieldReader;
19///Field `MWID` writer - MWID
20pub type MWID_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21///Field `FACCEN` reader - FACCEN
22pub type FACCEN_R = crate::BitReader;
23///Field `FACCEN` writer - FACCEN
24pub type FACCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `BURSTEN` reader - BURSTEN
26pub type BURSTEN_R = crate::BitReader;
27///Field `BURSTEN` writer - BURSTEN
28pub type BURSTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `WAITPOL` reader - WAITPOL
30pub type WAITPOL_R = crate::BitReader;
31///Field `WAITPOL` writer - WAITPOL
32pub type WAITPOL_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `WAITCFG` reader - WAITCFG
34pub type WAITCFG_R = crate::BitReader;
35///Field `WAITCFG` writer - WAITCFG
36pub type WAITCFG_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `WREN` reader - WREN
38pub type WREN_R = crate::BitReader;
39///Field `WREN` writer - WREN
40pub type WREN_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `WAITEN` reader - WAITEN
42pub type WAITEN_R = crate::BitReader;
43///Field `WAITEN` writer - WAITEN
44pub type WAITEN_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `EXTMOD` reader - EXTMOD
46pub type EXTMOD_R = crate::BitReader;
47///Field `EXTMOD` writer - EXTMOD
48pub type EXTMOD_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `ASYNCWAIT` reader - ASYNCWAIT
50pub type ASYNCWAIT_R = crate::BitReader;
51///Field `ASYNCWAIT` writer - ASYNCWAIT
52pub type ASYNCWAIT_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `CBURSTRW` reader - CBURSTRW
54pub type CBURSTRW_R = crate::BitReader;
55///Field `CBURSTRW` writer - CBURSTRW
56pub type CBURSTRW_W<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58    ///Bit 0 - MBKEN
59    #[inline(always)]
60    pub fn mbken(&self) -> MBKEN_R {
61        MBKEN_R::new((self.bits & 1) != 0)
62    }
63    ///Bit 1 - MUXEN
64    #[inline(always)]
65    pub fn muxen(&self) -> MUXEN_R {
66        MUXEN_R::new(((self.bits >> 1) & 1) != 0)
67    }
68    ///Bits 2:3 - MTYP
69    #[inline(always)]
70    pub fn mtyp(&self) -> MTYP_R {
71        MTYP_R::new(((self.bits >> 2) & 3) as u8)
72    }
73    ///Bits 4:5 - MWID
74    #[inline(always)]
75    pub fn mwid(&self) -> MWID_R {
76        MWID_R::new(((self.bits >> 4) & 3) as u8)
77    }
78    ///Bit 6 - FACCEN
79    #[inline(always)]
80    pub fn faccen(&self) -> FACCEN_R {
81        FACCEN_R::new(((self.bits >> 6) & 1) != 0)
82    }
83    ///Bit 8 - BURSTEN
84    #[inline(always)]
85    pub fn bursten(&self) -> BURSTEN_R {
86        BURSTEN_R::new(((self.bits >> 8) & 1) != 0)
87    }
88    ///Bit 9 - WAITPOL
89    #[inline(always)]
90    pub fn waitpol(&self) -> WAITPOL_R {
91        WAITPOL_R::new(((self.bits >> 9) & 1) != 0)
92    }
93    ///Bit 11 - WAITCFG
94    #[inline(always)]
95    pub fn waitcfg(&self) -> WAITCFG_R {
96        WAITCFG_R::new(((self.bits >> 11) & 1) != 0)
97    }
98    ///Bit 12 - WREN
99    #[inline(always)]
100    pub fn wren(&self) -> WREN_R {
101        WREN_R::new(((self.bits >> 12) & 1) != 0)
102    }
103    ///Bit 13 - WAITEN
104    #[inline(always)]
105    pub fn waiten(&self) -> WAITEN_R {
106        WAITEN_R::new(((self.bits >> 13) & 1) != 0)
107    }
108    ///Bit 14 - EXTMOD
109    #[inline(always)]
110    pub fn extmod(&self) -> EXTMOD_R {
111        EXTMOD_R::new(((self.bits >> 14) & 1) != 0)
112    }
113    ///Bit 15 - ASYNCWAIT
114    #[inline(always)]
115    pub fn asyncwait(&self) -> ASYNCWAIT_R {
116        ASYNCWAIT_R::new(((self.bits >> 15) & 1) != 0)
117    }
118    ///Bit 19 - CBURSTRW
119    #[inline(always)]
120    pub fn cburstrw(&self) -> CBURSTRW_R {
121        CBURSTRW_R::new(((self.bits >> 19) & 1) != 0)
122    }
123}
124impl core::fmt::Debug for R {
125    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
126        f.debug_struct("BCR1")
127            .field("cburstrw", &self.cburstrw())
128            .field("asyncwait", &self.asyncwait())
129            .field("extmod", &self.extmod())
130            .field("waiten", &self.waiten())
131            .field("wren", &self.wren())
132            .field("waitcfg", &self.waitcfg())
133            .field("waitpol", &self.waitpol())
134            .field("bursten", &self.bursten())
135            .field("faccen", &self.faccen())
136            .field("mwid", &self.mwid())
137            .field("mtyp", &self.mtyp())
138            .field("muxen", &self.muxen())
139            .field("mbken", &self.mbken())
140            .finish()
141    }
142}
143impl W {
144    ///Bit 0 - MBKEN
145    #[inline(always)]
146    pub fn mbken(&mut self) -> MBKEN_W<BCR1rs> {
147        MBKEN_W::new(self, 0)
148    }
149    ///Bit 1 - MUXEN
150    #[inline(always)]
151    pub fn muxen(&mut self) -> MUXEN_W<BCR1rs> {
152        MUXEN_W::new(self, 1)
153    }
154    ///Bits 2:3 - MTYP
155    #[inline(always)]
156    pub fn mtyp(&mut self) -> MTYP_W<BCR1rs> {
157        MTYP_W::new(self, 2)
158    }
159    ///Bits 4:5 - MWID
160    #[inline(always)]
161    pub fn mwid(&mut self) -> MWID_W<BCR1rs> {
162        MWID_W::new(self, 4)
163    }
164    ///Bit 6 - FACCEN
165    #[inline(always)]
166    pub fn faccen(&mut self) -> FACCEN_W<BCR1rs> {
167        FACCEN_W::new(self, 6)
168    }
169    ///Bit 8 - BURSTEN
170    #[inline(always)]
171    pub fn bursten(&mut self) -> BURSTEN_W<BCR1rs> {
172        BURSTEN_W::new(self, 8)
173    }
174    ///Bit 9 - WAITPOL
175    #[inline(always)]
176    pub fn waitpol(&mut self) -> WAITPOL_W<BCR1rs> {
177        WAITPOL_W::new(self, 9)
178    }
179    ///Bit 11 - WAITCFG
180    #[inline(always)]
181    pub fn waitcfg(&mut self) -> WAITCFG_W<BCR1rs> {
182        WAITCFG_W::new(self, 11)
183    }
184    ///Bit 12 - WREN
185    #[inline(always)]
186    pub fn wren(&mut self) -> WREN_W<BCR1rs> {
187        WREN_W::new(self, 12)
188    }
189    ///Bit 13 - WAITEN
190    #[inline(always)]
191    pub fn waiten(&mut self) -> WAITEN_W<BCR1rs> {
192        WAITEN_W::new(self, 13)
193    }
194    ///Bit 14 - EXTMOD
195    #[inline(always)]
196    pub fn extmod(&mut self) -> EXTMOD_W<BCR1rs> {
197        EXTMOD_W::new(self, 14)
198    }
199    ///Bit 15 - ASYNCWAIT
200    #[inline(always)]
201    pub fn asyncwait(&mut self) -> ASYNCWAIT_W<BCR1rs> {
202        ASYNCWAIT_W::new(self, 15)
203    }
204    ///Bit 19 - CBURSTRW
205    #[inline(always)]
206    pub fn cburstrw(&mut self) -> CBURSTRW_W<BCR1rs> {
207        CBURSTRW_W::new(self, 19)
208    }
209}
210/**SRAM/NOR-Flash chip-select control register 1
211
212You can [`read`](crate::Reg::read) this register and get [`bcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
213
214See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#FSMC:BCR1)*/
215pub struct BCR1rs;
216impl crate::RegisterSpec for BCR1rs {
217    type Ux = u32;
218}
219///`read()` method returns [`bcr1::R`](R) reader structure
220impl crate::Readable for BCR1rs {}
221///`write(|w| ..)` method takes [`bcr1::W`](W) writer structure
222impl crate::Writable for BCR1rs {
223    type Safety = crate::Unsafe;
224}
225///`reset()` method sets BCR1 to value 0x30d0
226impl crate::Resettable for BCR1rs {
227    const RESET_VALUE: u32 = 0x30d0;
228}
stm32f1_staging/stm32f107/fsmc/bcr1.rs

stm32f1_staging/stm32f107/fsmc/
bcr1.rs
