stm32f1_staging/stm32f107/exti/
rtsr.rs

1///Register `RTSR` reader
2pub type R = crate::R<RTSRrs>;
3///Register `RTSR` writer
4pub type W = crate::W<RTSRrs>;
5/**Rising trigger event configuration of line %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum RISING_TRIGGER {
11    ///0: Rising edge trigger is disabled
12    Disabled = 0,
13    ///1: Rising edge trigger is enabled
14    Enabled = 1,
15}
16impl From<RISING_TRIGGER> for bool {
17    #[inline(always)]
18    fn from(variant: RISING_TRIGGER) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `TR(0-19)` reader - Rising trigger event configuration of line %s
23pub type TR_R = crate::BitReader<RISING_TRIGGER>;
24impl TR_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> RISING_TRIGGER {
28        match self.bits {
29            false => RISING_TRIGGER::Disabled,
30            true => RISING_TRIGGER::Enabled,
31        }
32    }
33    ///Rising edge trigger is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == RISING_TRIGGER::Disabled
37    }
38    ///Rising edge trigger is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == RISING_TRIGGER::Enabled
42    }
43}
44///Field `TR(0-19)` writer - Rising trigger event configuration of line %s
45pub type TR_W<'a, REG> = crate::BitWriter<'a, REG, RISING_TRIGGER>;
46impl<'a, REG> TR_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Rising edge trigger is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(RISING_TRIGGER::Disabled)
54    }
55    ///Rising edge trigger is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(RISING_TRIGGER::Enabled)
59    }
60}
61impl R {
62    ///Rising trigger event configuration of line (0-19)
63    ///
64    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `TR0` field.</div>
65    #[inline(always)]
66    pub fn tr(&self, n: u8) -> TR_R {
67        #[allow(clippy::no_effect)] [(); 20][n as usize];
68        TR_R::new(((self.bits >> n) & 1) != 0)
69    }
70    ///Iterator for array of:
71    ///Rising trigger event configuration of line (0-19)
72    #[inline(always)]
73    pub fn tr_iter(&self) -> impl Iterator<Item = TR_R> + '_ {
74        (0..20).map(move |n| TR_R::new(((self.bits >> n) & 1) != 0))
75    }
76    ///Bit 0 - Rising trigger event configuration of line 0
77    #[inline(always)]
78    pub fn tr0(&self) -> TR_R {
79        TR_R::new((self.bits & 1) != 0)
80    }
81    ///Bit 1 - Rising trigger event configuration of line 1
82    #[inline(always)]
83    pub fn tr1(&self) -> TR_R {
84        TR_R::new(((self.bits >> 1) & 1) != 0)
85    }
86    ///Bit 2 - Rising trigger event configuration of line 2
87    #[inline(always)]
88    pub fn tr2(&self) -> TR_R {
89        TR_R::new(((self.bits >> 2) & 1) != 0)
90    }
91    ///Bit 3 - Rising trigger event configuration of line 3
92    #[inline(always)]
93    pub fn tr3(&self) -> TR_R {
94        TR_R::new(((self.bits >> 3) & 1) != 0)
95    }
96    ///Bit 4 - Rising trigger event configuration of line 4
97    #[inline(always)]
98    pub fn tr4(&self) -> TR_R {
99        TR_R::new(((self.bits >> 4) & 1) != 0)
100    }
101    ///Bit 5 - Rising trigger event configuration of line 5
102    #[inline(always)]
103    pub fn tr5(&self) -> TR_R {
104        TR_R::new(((self.bits >> 5) & 1) != 0)
105    }
106    ///Bit 6 - Rising trigger event configuration of line 6
107    #[inline(always)]
108    pub fn tr6(&self) -> TR_R {
109        TR_R::new(((self.bits >> 6) & 1) != 0)
110    }
111    ///Bit 7 - Rising trigger event configuration of line 7
112    #[inline(always)]
113    pub fn tr7(&self) -> TR_R {
114        TR_R::new(((self.bits >> 7) & 1) != 0)
115    }
116    ///Bit 8 - Rising trigger event configuration of line 8
117    #[inline(always)]
118    pub fn tr8(&self) -> TR_R {
119        TR_R::new(((self.bits >> 8) & 1) != 0)
120    }
121    ///Bit 9 - Rising trigger event configuration of line 9
122    #[inline(always)]
123    pub fn tr9(&self) -> TR_R {
124        TR_R::new(((self.bits >> 9) & 1) != 0)
125    }
126    ///Bit 10 - Rising trigger event configuration of line 10
127    #[inline(always)]
128    pub fn tr10(&self) -> TR_R {
129        TR_R::new(((self.bits >> 10) & 1) != 0)
130    }
131    ///Bit 11 - Rising trigger event configuration of line 11
132    #[inline(always)]
133    pub fn tr11(&self) -> TR_R {
134        TR_R::new(((self.bits >> 11) & 1) != 0)
135    }
136    ///Bit 12 - Rising trigger event configuration of line 12
137    #[inline(always)]
138    pub fn tr12(&self) -> TR_R {
139        TR_R::new(((self.bits >> 12) & 1) != 0)
140    }
141    ///Bit 13 - Rising trigger event configuration of line 13
142    #[inline(always)]
143    pub fn tr13(&self) -> TR_R {
144        TR_R::new(((self.bits >> 13) & 1) != 0)
145    }
146    ///Bit 14 - Rising trigger event configuration of line 14
147    #[inline(always)]
148    pub fn tr14(&self) -> TR_R {
149        TR_R::new(((self.bits >> 14) & 1) != 0)
150    }
151    ///Bit 15 - Rising trigger event configuration of line 15
152    #[inline(always)]
153    pub fn tr15(&self) -> TR_R {
154        TR_R::new(((self.bits >> 15) & 1) != 0)
155    }
156    ///Bit 16 - Rising trigger event configuration of line 16
157    #[inline(always)]
158    pub fn tr16(&self) -> TR_R {
159        TR_R::new(((self.bits >> 16) & 1) != 0)
160    }
161    ///Bit 17 - Rising trigger event configuration of line 17
162    #[inline(always)]
163    pub fn tr17(&self) -> TR_R {
164        TR_R::new(((self.bits >> 17) & 1) != 0)
165    }
166    ///Bit 18 - Rising trigger event configuration of line 18
167    #[inline(always)]
168    pub fn tr18(&self) -> TR_R {
169        TR_R::new(((self.bits >> 18) & 1) != 0)
170    }
171    ///Bit 19 - Rising trigger event configuration of line 19
172    #[inline(always)]
173    pub fn tr19(&self) -> TR_R {
174        TR_R::new(((self.bits >> 19) & 1) != 0)
175    }
176}
177impl core::fmt::Debug for R {
178    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
179        f.debug_struct("RTSR")
180            .field("tr0", &self.tr0())
181            .field("tr1", &self.tr1())
182            .field("tr2", &self.tr2())
183            .field("tr3", &self.tr3())
184            .field("tr4", &self.tr4())
185            .field("tr5", &self.tr5())
186            .field("tr6", &self.tr6())
187            .field("tr7", &self.tr7())
188            .field("tr8", &self.tr8())
189            .field("tr9", &self.tr9())
190            .field("tr10", &self.tr10())
191            .field("tr11", &self.tr11())
192            .field("tr12", &self.tr12())
193            .field("tr13", &self.tr13())
194            .field("tr14", &self.tr14())
195            .field("tr15", &self.tr15())
196            .field("tr16", &self.tr16())
197            .field("tr17", &self.tr17())
198            .field("tr18", &self.tr18())
199            .field("tr19", &self.tr19())
200            .finish()
201    }
202}
203impl W {
204    ///Rising trigger event configuration of line (0-19)
205    ///
206    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `TR0` field.</div>
207    #[inline(always)]
208    pub fn tr(&mut self, n: u8) -> TR_W<RTSRrs> {
209        #[allow(clippy::no_effect)] [(); 20][n as usize];
210        TR_W::new(self, n)
211    }
212    ///Bit 0 - Rising trigger event configuration of line 0
213    #[inline(always)]
214    pub fn tr0(&mut self) -> TR_W<RTSRrs> {
215        TR_W::new(self, 0)
216    }
217    ///Bit 1 - Rising trigger event configuration of line 1
218    #[inline(always)]
219    pub fn tr1(&mut self) -> TR_W<RTSRrs> {
220        TR_W::new(self, 1)
221    }
222    ///Bit 2 - Rising trigger event configuration of line 2
223    #[inline(always)]
224    pub fn tr2(&mut self) -> TR_W<RTSRrs> {
225        TR_W::new(self, 2)
226    }
227    ///Bit 3 - Rising trigger event configuration of line 3
228    #[inline(always)]
229    pub fn tr3(&mut self) -> TR_W<RTSRrs> {
230        TR_W::new(self, 3)
231    }
232    ///Bit 4 - Rising trigger event configuration of line 4
233    #[inline(always)]
234    pub fn tr4(&mut self) -> TR_W<RTSRrs> {
235        TR_W::new(self, 4)
236    }
237    ///Bit 5 - Rising trigger event configuration of line 5
238    #[inline(always)]
239    pub fn tr5(&mut self) -> TR_W<RTSRrs> {
240        TR_W::new(self, 5)
241    }
242    ///Bit 6 - Rising trigger event configuration of line 6
243    #[inline(always)]
244    pub fn tr6(&mut self) -> TR_W<RTSRrs> {
245        TR_W::new(self, 6)
246    }
247    ///Bit 7 - Rising trigger event configuration of line 7
248    #[inline(always)]
249    pub fn tr7(&mut self) -> TR_W<RTSRrs> {
250        TR_W::new(self, 7)
251    }
252    ///Bit 8 - Rising trigger event configuration of line 8
253    #[inline(always)]
254    pub fn tr8(&mut self) -> TR_W<RTSRrs> {
255        TR_W::new(self, 8)
256    }
257    ///Bit 9 - Rising trigger event configuration of line 9
258    #[inline(always)]
259    pub fn tr9(&mut self) -> TR_W<RTSRrs> {
260        TR_W::new(self, 9)
261    }
262    ///Bit 10 - Rising trigger event configuration of line 10
263    #[inline(always)]
264    pub fn tr10(&mut self) -> TR_W<RTSRrs> {
265        TR_W::new(self, 10)
266    }
267    ///Bit 11 - Rising trigger event configuration of line 11
268    #[inline(always)]
269    pub fn tr11(&mut self) -> TR_W<RTSRrs> {
270        TR_W::new(self, 11)
271    }
272    ///Bit 12 - Rising trigger event configuration of line 12
273    #[inline(always)]
274    pub fn tr12(&mut self) -> TR_W<RTSRrs> {
275        TR_W::new(self, 12)
276    }
277    ///Bit 13 - Rising trigger event configuration of line 13
278    #[inline(always)]
279    pub fn tr13(&mut self) -> TR_W<RTSRrs> {
280        TR_W::new(self, 13)
281    }
282    ///Bit 14 - Rising trigger event configuration of line 14
283    #[inline(always)]
284    pub fn tr14(&mut self) -> TR_W<RTSRrs> {
285        TR_W::new(self, 14)
286    }
287    ///Bit 15 - Rising trigger event configuration of line 15
288    #[inline(always)]
289    pub fn tr15(&mut self) -> TR_W<RTSRrs> {
290        TR_W::new(self, 15)
291    }
292    ///Bit 16 - Rising trigger event configuration of line 16
293    #[inline(always)]
294    pub fn tr16(&mut self) -> TR_W<RTSRrs> {
295        TR_W::new(self, 16)
296    }
297    ///Bit 17 - Rising trigger event configuration of line 17
298    #[inline(always)]
299    pub fn tr17(&mut self) -> TR_W<RTSRrs> {
300        TR_W::new(self, 17)
301    }
302    ///Bit 18 - Rising trigger event configuration of line 18
303    #[inline(always)]
304    pub fn tr18(&mut self) -> TR_W<RTSRrs> {
305        TR_W::new(self, 18)
306    }
307    ///Bit 19 - Rising trigger event configuration of line 19
308    #[inline(always)]
309    pub fn tr19(&mut self) -> TR_W<RTSRrs> {
310        TR_W::new(self, 19)
311    }
312}
313/**Rising Trigger selection register (EXTI_RTSR)
314
315You can [`read`](crate::Reg::read) this register and get [`rtsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
316
317See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#EXTI:RTSR)*/
318pub struct RTSRrs;
319impl crate::RegisterSpec for RTSRrs {
320    type Ux = u32;
321}
322///`read()` method returns [`rtsr::R`](R) reader structure
323impl crate::Readable for RTSRrs {}
324///`write(|w| ..)` method takes [`rtsr::W`](W) writer structure
325impl crate::Writable for RTSRrs {
326    type Safety = crate::Unsafe;
327}
328///`reset()` method sets RTSR to value 0
329impl crate::Resettable for RTSRrs {}
stm32f1_staging/stm32f107/exti/rtsr.rs

stm32f1_staging/stm32f107/exti/
rtsr.rs
