stm32f1_staging/stm32f107/dbgmcu/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5///Field `DBG_SLEEP` reader - DBG_SLEEP
6pub type DBG_SLEEP_R = crate::BitReader;
7///Field `DBG_SLEEP` writer - DBG_SLEEP
8pub type DBG_SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DBG_STOP` reader - DBG_STOP
10pub type DBG_STOP_R = crate::BitReader;
11///Field `DBG_STOP` writer - DBG_STOP
12pub type DBG_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `DBG_STANDBY` reader - DBG_STANDBY
14pub type DBG_STANDBY_R = crate::BitReader;
15///Field `DBG_STANDBY` writer - DBG_STANDBY
16pub type DBG_STANDBY_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `TRACE_IOEN` reader - TRACE_IOEN
18pub type TRACE_IOEN_R = crate::BitReader;
19///Field `TRACE_IOEN` writer - TRACE_IOEN
20pub type TRACE_IOEN_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `TRACE_MODE` reader - TRACE_MODE
22pub type TRACE_MODE_R = crate::FieldReader;
23///Field `TRACE_MODE` writer - TRACE_MODE
24pub type TRACE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25///Field `DBG_IWDG_STOP` reader - DBG_IWDG_STOP
26pub type DBG_IWDG_STOP_R = crate::BitReader;
27///Field `DBG_IWDG_STOP` writer - DBG_IWDG_STOP
28pub type DBG_IWDG_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP
30pub type DBG_WWDG_STOP_R = crate::BitReader;
31///Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP
32pub type DBG_WWDG_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `DBG_TIM1_STOP` reader - DBG_TIM1_STOP
34pub type DBG_TIM1_STOP_R = crate::BitReader;
35///Field `DBG_TIM1_STOP` writer - DBG_TIM1_STOP
36pub type DBG_TIM1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP
38pub type DBG_TIM2_STOP_R = crate::BitReader;
39///Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP
40pub type DBG_TIM2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `DBG_TIM3_STOP` reader - DBG_TIM3_STOP
42pub type DBG_TIM3_STOP_R = crate::BitReader;
43///Field `DBG_TIM3_STOP` writer - DBG_TIM3_STOP
44pub type DBG_TIM3_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP
46pub type DBG_TIM4_STOP_R = crate::BitReader;
47///Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP
48pub type DBG_TIM4_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP
50pub type DBG_CAN1_STOP_R = crate::BitReader;
51///Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP
52pub type DBG_CAN1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `DBG_I2C1_SMBUS_TIMEOUT` reader - DBG_I2C1_SMBUS_TIMEOUT
54pub type DBG_I2C1_SMBUS_TIMEOUT_R = crate::BitReader;
55///Field `DBG_I2C1_SMBUS_TIMEOUT` writer - DBG_I2C1_SMBUS_TIMEOUT
56pub type DBG_I2C1_SMBUS_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
57///Field `DBG_I2C2_SMBUS_TIMEOUT` reader - DBG_I2C2_SMBUS_TIMEOUT
58pub type DBG_I2C2_SMBUS_TIMEOUT_R = crate::BitReader;
59///Field `DBG_I2C2_SMBUS_TIMEOUT` writer - DBG_I2C2_SMBUS_TIMEOUT
60pub type DBG_I2C2_SMBUS_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
61///Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP
62pub type DBG_TIM5_STOP_R = crate::BitReader;
63///Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP
64pub type DBG_TIM5_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
65///Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP
66pub type DBG_TIM6_STOP_R = crate::BitReader;
67///Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP
68pub type DBG_TIM6_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
69///Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP
70pub type DBG_TIM7_STOP_R = crate::BitReader;
71///Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP
72pub type DBG_TIM7_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
73///Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP
74pub type DBG_CAN2_STOP_R = crate::BitReader;
75///Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP
76pub type DBG_CAN2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
77impl R {
78    ///Bit 0 - DBG_SLEEP
79    #[inline(always)]
80    pub fn dbg_sleep(&self) -> DBG_SLEEP_R {
81        DBG_SLEEP_R::new((self.bits & 1) != 0)
82    }
83    ///Bit 1 - DBG_STOP
84    #[inline(always)]
85    pub fn dbg_stop(&self) -> DBG_STOP_R {
86        DBG_STOP_R::new(((self.bits >> 1) & 1) != 0)
87    }
88    ///Bit 2 - DBG_STANDBY
89    #[inline(always)]
90    pub fn dbg_standby(&self) -> DBG_STANDBY_R {
91        DBG_STANDBY_R::new(((self.bits >> 2) & 1) != 0)
92    }
93    ///Bit 5 - TRACE_IOEN
94    #[inline(always)]
95    pub fn trace_ioen(&self) -> TRACE_IOEN_R {
96        TRACE_IOEN_R::new(((self.bits >> 5) & 1) != 0)
97    }
98    ///Bits 6:7 - TRACE_MODE
99    #[inline(always)]
100    pub fn trace_mode(&self) -> TRACE_MODE_R {
101        TRACE_MODE_R::new(((self.bits >> 6) & 3) as u8)
102    }
103    ///Bit 8 - DBG_IWDG_STOP
104    #[inline(always)]
105    pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R {
106        DBG_IWDG_STOP_R::new(((self.bits >> 8) & 1) != 0)
107    }
108    ///Bit 9 - DBG_WWDG_STOP
109    #[inline(always)]
110    pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R {
111        DBG_WWDG_STOP_R::new(((self.bits >> 9) & 1) != 0)
112    }
113    ///Bit 10 - DBG_TIM1_STOP
114    #[inline(always)]
115    pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R {
116        DBG_TIM1_STOP_R::new(((self.bits >> 10) & 1) != 0)
117    }
118    ///Bit 11 - DBG_TIM2_STOP
119    #[inline(always)]
120    pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R {
121        DBG_TIM2_STOP_R::new(((self.bits >> 11) & 1) != 0)
122    }
123    ///Bit 12 - DBG_TIM3_STOP
124    #[inline(always)]
125    pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R {
126        DBG_TIM3_STOP_R::new(((self.bits >> 12) & 1) != 0)
127    }
128    ///Bit 13 - DBG_TIM4_STOP
129    #[inline(always)]
130    pub fn dbg_tim4_stop(&self) -> DBG_TIM4_STOP_R {
131        DBG_TIM4_STOP_R::new(((self.bits >> 13) & 1) != 0)
132    }
133    ///Bit 14 - DBG_CAN1_STOP
134    #[inline(always)]
135    pub fn dbg_can1_stop(&self) -> DBG_CAN1_STOP_R {
136        DBG_CAN1_STOP_R::new(((self.bits >> 14) & 1) != 0)
137    }
138    ///Bit 15 - DBG_I2C1_SMBUS_TIMEOUT
139    #[inline(always)]
140    pub fn dbg_i2c1_smbus_timeout(&self) -> DBG_I2C1_SMBUS_TIMEOUT_R {
141        DBG_I2C1_SMBUS_TIMEOUT_R::new(((self.bits >> 15) & 1) != 0)
142    }
143    ///Bit 16 - DBG_I2C2_SMBUS_TIMEOUT
144    #[inline(always)]
145    pub fn dbg_i2c2_smbus_timeout(&self) -> DBG_I2C2_SMBUS_TIMEOUT_R {
146        DBG_I2C2_SMBUS_TIMEOUT_R::new(((self.bits >> 16) & 1) != 0)
147    }
148    ///Bit 18 - DBG_TIM5_STOP
149    #[inline(always)]
150    pub fn dbg_tim5_stop(&self) -> DBG_TIM5_STOP_R {
151        DBG_TIM5_STOP_R::new(((self.bits >> 18) & 1) != 0)
152    }
153    ///Bit 19 - DBG_TIM6_STOP
154    #[inline(always)]
155    pub fn dbg_tim6_stop(&self) -> DBG_TIM6_STOP_R {
156        DBG_TIM6_STOP_R::new(((self.bits >> 19) & 1) != 0)
157    }
158    ///Bit 20 - DBG_TIM7_STOP
159    #[inline(always)]
160    pub fn dbg_tim7_stop(&self) -> DBG_TIM7_STOP_R {
161        DBG_TIM7_STOP_R::new(((self.bits >> 20) & 1) != 0)
162    }
163    ///Bit 21 - DBG_CAN2_STOP
164    #[inline(always)]
165    pub fn dbg_can2_stop(&self) -> DBG_CAN2_STOP_R {
166        DBG_CAN2_STOP_R::new(((self.bits >> 21) & 1) != 0)
167    }
168}
169impl core::fmt::Debug for R {
170    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
171        f.debug_struct("CR")
172            .field("dbg_sleep", &self.dbg_sleep())
173            .field("dbg_stop", &self.dbg_stop())
174            .field("dbg_standby", &self.dbg_standby())
175            .field("trace_ioen", &self.trace_ioen())
176            .field("trace_mode", &self.trace_mode())
177            .field("dbg_iwdg_stop", &self.dbg_iwdg_stop())
178            .field("dbg_wwdg_stop", &self.dbg_wwdg_stop())
179            .field("dbg_tim1_stop", &self.dbg_tim1_stop())
180            .field("dbg_tim2_stop", &self.dbg_tim2_stop())
181            .field("dbg_tim3_stop", &self.dbg_tim3_stop())
182            .field("dbg_tim4_stop", &self.dbg_tim4_stop())
183            .field("dbg_can1_stop", &self.dbg_can1_stop())
184            .field("dbg_i2c1_smbus_timeout", &self.dbg_i2c1_smbus_timeout())
185            .field("dbg_i2c2_smbus_timeout", &self.dbg_i2c2_smbus_timeout())
186            .field("dbg_tim5_stop", &self.dbg_tim5_stop())
187            .field("dbg_tim6_stop", &self.dbg_tim6_stop())
188            .field("dbg_tim7_stop", &self.dbg_tim7_stop())
189            .field("dbg_can2_stop", &self.dbg_can2_stop())
190            .finish()
191    }
192}
193impl W {
194    ///Bit 0 - DBG_SLEEP
195    #[inline(always)]
196    pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<CRrs> {
197        DBG_SLEEP_W::new(self, 0)
198    }
199    ///Bit 1 - DBG_STOP
200    #[inline(always)]
201    pub fn dbg_stop(&mut self) -> DBG_STOP_W<CRrs> {
202        DBG_STOP_W::new(self, 1)
203    }
204    ///Bit 2 - DBG_STANDBY
205    #[inline(always)]
206    pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<CRrs> {
207        DBG_STANDBY_W::new(self, 2)
208    }
209    ///Bit 5 - TRACE_IOEN
210    #[inline(always)]
211    pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<CRrs> {
212        TRACE_IOEN_W::new(self, 5)
213    }
214    ///Bits 6:7 - TRACE_MODE
215    #[inline(always)]
216    pub fn trace_mode(&mut self) -> TRACE_MODE_W<CRrs> {
217        TRACE_MODE_W::new(self, 6)
218    }
219    ///Bit 8 - DBG_IWDG_STOP
220    #[inline(always)]
221    pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<CRrs> {
222        DBG_IWDG_STOP_W::new(self, 8)
223    }
224    ///Bit 9 - DBG_WWDG_STOP
225    #[inline(always)]
226    pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<CRrs> {
227        DBG_WWDG_STOP_W::new(self, 9)
228    }
229    ///Bit 10 - DBG_TIM1_STOP
230    #[inline(always)]
231    pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<CRrs> {
232        DBG_TIM1_STOP_W::new(self, 10)
233    }
234    ///Bit 11 - DBG_TIM2_STOP
235    #[inline(always)]
236    pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<CRrs> {
237        DBG_TIM2_STOP_W::new(self, 11)
238    }
239    ///Bit 12 - DBG_TIM3_STOP
240    #[inline(always)]
241    pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<CRrs> {
242        DBG_TIM3_STOP_W::new(self, 12)
243    }
244    ///Bit 13 - DBG_TIM4_STOP
245    #[inline(always)]
246    pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<CRrs> {
247        DBG_TIM4_STOP_W::new(self, 13)
248    }
249    ///Bit 14 - DBG_CAN1_STOP
250    #[inline(always)]
251    pub fn dbg_can1_stop(&mut self) -> DBG_CAN1_STOP_W<CRrs> {
252        DBG_CAN1_STOP_W::new(self, 14)
253    }
254    ///Bit 15 - DBG_I2C1_SMBUS_TIMEOUT
255    #[inline(always)]
256    pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<CRrs> {
257        DBG_I2C1_SMBUS_TIMEOUT_W::new(self, 15)
258    }
259    ///Bit 16 - DBG_I2C2_SMBUS_TIMEOUT
260    #[inline(always)]
261    pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W<CRrs> {
262        DBG_I2C2_SMBUS_TIMEOUT_W::new(self, 16)
263    }
264    ///Bit 18 - DBG_TIM5_STOP
265    #[inline(always)]
266    pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<CRrs> {
267        DBG_TIM5_STOP_W::new(self, 18)
268    }
269    ///Bit 19 - DBG_TIM6_STOP
270    #[inline(always)]
271    pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<CRrs> {
272        DBG_TIM6_STOP_W::new(self, 19)
273    }
274    ///Bit 20 - DBG_TIM7_STOP
275    #[inline(always)]
276    pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<CRrs> {
277        DBG_TIM7_STOP_W::new(self, 20)
278    }
279    ///Bit 21 - DBG_CAN2_STOP
280    #[inline(always)]
281    pub fn dbg_can2_stop(&mut self) -> DBG_CAN2_STOP_W<CRrs> {
282        DBG_CAN2_STOP_W::new(self, 21)
283    }
284}
285/**DBGMCU_CR
286
287You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
288
289See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#DBGMCU:CR)*/
290pub struct CRrs;
291impl crate::RegisterSpec for CRrs {
292    type Ux = u32;
293}
294///`read()` method returns [`cr::R`](R) reader structure
295impl crate::Readable for CRrs {}
296///`write(|w| ..)` method takes [`cr::W`](W) writer structure
297impl crate::Writable for CRrs {
298    type Safety = crate::Unsafe;
299}
300///`reset()` method sets CR to value 0
301impl crate::Resettable for CRrs {}
stm32f1_staging/stm32f107/dbgmcu/cr.rs

stm32f1_staging/stm32f107/dbgmcu/
cr.rs
