stm32f1_staging/stm32f107/afio/
mapr.rs

1///Register `MAPR` reader
2pub type R = crate::R<MAPRrs>;
3///Register `MAPR` writer
4pub type W = crate::W<MAPRrs>;
5///Field `SPI1_REMAP` reader - SPI1 remapping
6pub type SPI1_REMAP_R = crate::BitReader;
7///Field `SPI1_REMAP` writer - SPI1 remapping
8pub type SPI1_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `I2C1_REMAP` reader - I2C1 remapping
10pub type I2C1_REMAP_R = crate::BitReader;
11///Field `I2C1_REMAP` writer - I2C1 remapping
12pub type I2C1_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `USART1_REMAP` reader - USART1 remapping
14pub type USART1_REMAP_R = crate::BitReader;
15///Field `USART1_REMAP` writer - USART1 remapping
16pub type USART1_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `USART2_REMAP` reader - USART2 remapping
18pub type USART2_REMAP_R = crate::BitReader;
19///Field `USART2_REMAP` writer - USART2 remapping
20pub type USART2_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `USART3_REMAP` reader - USART3 remapping
22pub type USART3_REMAP_R = crate::FieldReader;
23///Field `USART3_REMAP` writer - USART3 remapping
24pub type USART3_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25///Field `TIM1_REMAP` reader - TIM1 remapping
26pub type TIM1_REMAP_R = crate::FieldReader;
27///Field `TIM1_REMAP` writer - TIM1 remapping
28pub type TIM1_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29///Field `TIM2_REMAP` reader - TIM2 remapping
30pub type TIM2_REMAP_R = crate::FieldReader;
31///Field `TIM2_REMAP` writer - TIM2 remapping
32pub type TIM2_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33///Field `TIM3_REMAP` reader - TIM3 remapping
34pub type TIM3_REMAP_R = crate::FieldReader;
35///Field `TIM3_REMAP` writer - TIM3 remapping
36pub type TIM3_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37///Field `TIM4_REMAP` reader - TIM4 remapping
38pub type TIM4_REMAP_R = crate::BitReader;
39///Field `TIM4_REMAP` writer - TIM4 remapping
40pub type TIM4_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `CAN1_REMAP` reader - CAN1 remapping
42pub type CAN1_REMAP_R = crate::FieldReader;
43///Field `CAN1_REMAP` writer - CAN1 remapping
44pub type CAN1_REMAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
45///Field `PD01_REMAP` reader - Port D0/Port D1 mapping on OSCIN/OSCOUT
46pub type PD01_REMAP_R = crate::BitReader;
47///Field `PD01_REMAP` writer - Port D0/Port D1 mapping on OSCIN/OSCOUT
48pub type PD01_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `TIM5CH4_IREMAP` reader - Set and cleared by software
50pub type TIM5CH4_IREMAP_R = crate::BitReader;
51///Field `TIM5CH4_IREMAP` writer - Set and cleared by software
52pub type TIM5CH4_IREMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `ETH_REMAP` reader - Ethernet MAC I/O remapping
54pub type ETH_REMAP_R = crate::BitReader;
55///Field `ETH_REMAP` writer - Ethernet MAC I/O remapping
56pub type ETH_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
57///Field `CAN2_REMAP` reader - CAN2 I/O remapping
58pub type CAN2_REMAP_R = crate::BitReader;
59///Field `CAN2_REMAP` writer - CAN2 I/O remapping
60pub type CAN2_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
61///Field `MII_RMII_SEL` reader - MII or RMII selection
62pub type MII_RMII_SEL_R = crate::BitReader;
63///Field `MII_RMII_SEL` writer - MII or RMII selection
64pub type MII_RMII_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
65///Field `SWJ_CFG` writer - Serial wire JTAG configuration
66pub type SWJ_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
67///Field `SPI3_REMAP` reader - SPI3/I2S3 remapping
68pub type SPI3_REMAP_R = crate::BitReader;
69///Field `SPI3_REMAP` writer - SPI3/I2S3 remapping
70pub type SPI3_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
71///Field `TIM2ITR1_IREMAP` reader - TIM2 internal trigger 1 remapping
72pub type TIM2ITR1_IREMAP_R = crate::BitReader;
73///Field `TIM2ITR1_IREMAP` writer - TIM2 internal trigger 1 remapping
74pub type TIM2ITR1_IREMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
75///Field `PTP_PPS_REMAP` reader - Ethernet PTP PPS remapping
76pub type PTP_PPS_REMAP_R = crate::BitReader;
77///Field `PTP_PPS_REMAP` writer - Ethernet PTP PPS remapping
78pub type PTP_PPS_REMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
79impl R {
80    ///Bit 0 - SPI1 remapping
81    #[inline(always)]
82    pub fn spi1_remap(&self) -> SPI1_REMAP_R {
83        SPI1_REMAP_R::new((self.bits & 1) != 0)
84    }
85    ///Bit 1 - I2C1 remapping
86    #[inline(always)]
87    pub fn i2c1_remap(&self) -> I2C1_REMAP_R {
88        I2C1_REMAP_R::new(((self.bits >> 1) & 1) != 0)
89    }
90    ///Bit 2 - USART1 remapping
91    #[inline(always)]
92    pub fn usart1_remap(&self) -> USART1_REMAP_R {
93        USART1_REMAP_R::new(((self.bits >> 2) & 1) != 0)
94    }
95    ///Bit 3 - USART2 remapping
96    #[inline(always)]
97    pub fn usart2_remap(&self) -> USART2_REMAP_R {
98        USART2_REMAP_R::new(((self.bits >> 3) & 1) != 0)
99    }
100    ///Bits 4:5 - USART3 remapping
101    #[inline(always)]
102    pub fn usart3_remap(&self) -> USART3_REMAP_R {
103        USART3_REMAP_R::new(((self.bits >> 4) & 3) as u8)
104    }
105    ///Bits 6:7 - TIM1 remapping
106    #[inline(always)]
107    pub fn tim1_remap(&self) -> TIM1_REMAP_R {
108        TIM1_REMAP_R::new(((self.bits >> 6) & 3) as u8)
109    }
110    ///Bits 8:9 - TIM2 remapping
111    #[inline(always)]
112    pub fn tim2_remap(&self) -> TIM2_REMAP_R {
113        TIM2_REMAP_R::new(((self.bits >> 8) & 3) as u8)
114    }
115    ///Bits 10:11 - TIM3 remapping
116    #[inline(always)]
117    pub fn tim3_remap(&self) -> TIM3_REMAP_R {
118        TIM3_REMAP_R::new(((self.bits >> 10) & 3) as u8)
119    }
120    ///Bit 12 - TIM4 remapping
121    #[inline(always)]
122    pub fn tim4_remap(&self) -> TIM4_REMAP_R {
123        TIM4_REMAP_R::new(((self.bits >> 12) & 1) != 0)
124    }
125    ///Bits 13:14 - CAN1 remapping
126    #[inline(always)]
127    pub fn can1_remap(&self) -> CAN1_REMAP_R {
128        CAN1_REMAP_R::new(((self.bits >> 13) & 3) as u8)
129    }
130    ///Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT
131    #[inline(always)]
132    pub fn pd01_remap(&self) -> PD01_REMAP_R {
133        PD01_REMAP_R::new(((self.bits >> 15) & 1) != 0)
134    }
135    ///Bit 16 - Set and cleared by software
136    #[inline(always)]
137    pub fn tim5ch4_iremap(&self) -> TIM5CH4_IREMAP_R {
138        TIM5CH4_IREMAP_R::new(((self.bits >> 16) & 1) != 0)
139    }
140    ///Bit 21 - Ethernet MAC I/O remapping
141    #[inline(always)]
142    pub fn eth_remap(&self) -> ETH_REMAP_R {
143        ETH_REMAP_R::new(((self.bits >> 21) & 1) != 0)
144    }
145    ///Bit 22 - CAN2 I/O remapping
146    #[inline(always)]
147    pub fn can2_remap(&self) -> CAN2_REMAP_R {
148        CAN2_REMAP_R::new(((self.bits >> 22) & 1) != 0)
149    }
150    ///Bit 23 - MII or RMII selection
151    #[inline(always)]
152    pub fn mii_rmii_sel(&self) -> MII_RMII_SEL_R {
153        MII_RMII_SEL_R::new(((self.bits >> 23) & 1) != 0)
154    }
155    ///Bit 28 - SPI3/I2S3 remapping
156    #[inline(always)]
157    pub fn spi3_remap(&self) -> SPI3_REMAP_R {
158        SPI3_REMAP_R::new(((self.bits >> 28) & 1) != 0)
159    }
160    ///Bit 29 - TIM2 internal trigger 1 remapping
161    #[inline(always)]
162    pub fn tim2itr1_iremap(&self) -> TIM2ITR1_IREMAP_R {
163        TIM2ITR1_IREMAP_R::new(((self.bits >> 29) & 1) != 0)
164    }
165    ///Bit 30 - Ethernet PTP PPS remapping
166    #[inline(always)]
167    pub fn ptp_pps_remap(&self) -> PTP_PPS_REMAP_R {
168        PTP_PPS_REMAP_R::new(((self.bits >> 30) & 1) != 0)
169    }
170}
171impl core::fmt::Debug for R {
172    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
173        f.debug_struct("MAPR")
174            .field("spi1_remap", &self.spi1_remap())
175            .field("i2c1_remap", &self.i2c1_remap())
176            .field("usart1_remap", &self.usart1_remap())
177            .field("usart2_remap", &self.usart2_remap())
178            .field("usart3_remap", &self.usart3_remap())
179            .field("tim1_remap", &self.tim1_remap())
180            .field("tim2_remap", &self.tim2_remap())
181            .field("tim3_remap", &self.tim3_remap())
182            .field("tim4_remap", &self.tim4_remap())
183            .field("can1_remap", &self.can1_remap())
184            .field("pd01_remap", &self.pd01_remap())
185            .field("tim5ch4_iremap", &self.tim5ch4_iremap())
186            .field("eth_remap", &self.eth_remap())
187            .field("can2_remap", &self.can2_remap())
188            .field("mii_rmii_sel", &self.mii_rmii_sel())
189            .field("spi3_remap", &self.spi3_remap())
190            .field("tim2itr1_iremap", &self.tim2itr1_iremap())
191            .field("ptp_pps_remap", &self.ptp_pps_remap())
192            .finish()
193    }
194}
195impl W {
196    ///Bit 0 - SPI1 remapping
197    #[inline(always)]
198    pub fn spi1_remap(&mut self) -> SPI1_REMAP_W<MAPRrs> {
199        SPI1_REMAP_W::new(self, 0)
200    }
201    ///Bit 1 - I2C1 remapping
202    #[inline(always)]
203    pub fn i2c1_remap(&mut self) -> I2C1_REMAP_W<MAPRrs> {
204        I2C1_REMAP_W::new(self, 1)
205    }
206    ///Bit 2 - USART1 remapping
207    #[inline(always)]
208    pub fn usart1_remap(&mut self) -> USART1_REMAP_W<MAPRrs> {
209        USART1_REMAP_W::new(self, 2)
210    }
211    ///Bit 3 - USART2 remapping
212    #[inline(always)]
213    pub fn usart2_remap(&mut self) -> USART2_REMAP_W<MAPRrs> {
214        USART2_REMAP_W::new(self, 3)
215    }
216    ///Bits 4:5 - USART3 remapping
217    #[inline(always)]
218    pub fn usart3_remap(&mut self) -> USART3_REMAP_W<MAPRrs> {
219        USART3_REMAP_W::new(self, 4)
220    }
221    ///Bits 6:7 - TIM1 remapping
222    #[inline(always)]
223    pub fn tim1_remap(&mut self) -> TIM1_REMAP_W<MAPRrs> {
224        TIM1_REMAP_W::new(self, 6)
225    }
226    ///Bits 8:9 - TIM2 remapping
227    #[inline(always)]
228    pub fn tim2_remap(&mut self) -> TIM2_REMAP_W<MAPRrs> {
229        TIM2_REMAP_W::new(self, 8)
230    }
231    ///Bits 10:11 - TIM3 remapping
232    #[inline(always)]
233    pub fn tim3_remap(&mut self) -> TIM3_REMAP_W<MAPRrs> {
234        TIM3_REMAP_W::new(self, 10)
235    }
236    ///Bit 12 - TIM4 remapping
237    #[inline(always)]
238    pub fn tim4_remap(&mut self) -> TIM4_REMAP_W<MAPRrs> {
239        TIM4_REMAP_W::new(self, 12)
240    }
241    ///Bits 13:14 - CAN1 remapping
242    #[inline(always)]
243    pub fn can1_remap(&mut self) -> CAN1_REMAP_W<MAPRrs> {
244        CAN1_REMAP_W::new(self, 13)
245    }
246    ///Bit 15 - Port D0/Port D1 mapping on OSCIN/OSCOUT
247    #[inline(always)]
248    pub fn pd01_remap(&mut self) -> PD01_REMAP_W<MAPRrs> {
249        PD01_REMAP_W::new(self, 15)
250    }
251    ///Bit 16 - Set and cleared by software
252    #[inline(always)]
253    pub fn tim5ch4_iremap(&mut self) -> TIM5CH4_IREMAP_W<MAPRrs> {
254        TIM5CH4_IREMAP_W::new(self, 16)
255    }
256    ///Bit 21 - Ethernet MAC I/O remapping
257    #[inline(always)]
258    pub fn eth_remap(&mut self) -> ETH_REMAP_W<MAPRrs> {
259        ETH_REMAP_W::new(self, 21)
260    }
261    ///Bit 22 - CAN2 I/O remapping
262    #[inline(always)]
263    pub fn can2_remap(&mut self) -> CAN2_REMAP_W<MAPRrs> {
264        CAN2_REMAP_W::new(self, 22)
265    }
266    ///Bit 23 - MII or RMII selection
267    #[inline(always)]
268    pub fn mii_rmii_sel(&mut self) -> MII_RMII_SEL_W<MAPRrs> {
269        MII_RMII_SEL_W::new(self, 23)
270    }
271    ///Bits 24:26 - Serial wire JTAG configuration
272    #[inline(always)]
273    pub fn swj_cfg(&mut self) -> SWJ_CFG_W<MAPRrs> {
274        SWJ_CFG_W::new(self, 24)
275    }
276    ///Bit 28 - SPI3/I2S3 remapping
277    #[inline(always)]
278    pub fn spi3_remap(&mut self) -> SPI3_REMAP_W<MAPRrs> {
279        SPI3_REMAP_W::new(self, 28)
280    }
281    ///Bit 29 - TIM2 internal trigger 1 remapping
282    #[inline(always)]
283    pub fn tim2itr1_iremap(&mut self) -> TIM2ITR1_IREMAP_W<MAPRrs> {
284        TIM2ITR1_IREMAP_W::new(self, 29)
285    }
286    ///Bit 30 - Ethernet PTP PPS remapping
287    #[inline(always)]
288    pub fn ptp_pps_remap(&mut self) -> PTP_PPS_REMAP_W<MAPRrs> {
289        PTP_PPS_REMAP_W::new(self, 30)
290    }
291}
292/**AF remap and debug I/O configuration register (AFIO_MAPR)
293
294You can [`read`](crate::Reg::read) this register and get [`mapr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mapr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
295
296See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#AFIO:MAPR)*/
297pub struct MAPRrs;
298impl crate::RegisterSpec for MAPRrs {
299    type Ux = u32;
300}
301///`read()` method returns [`mapr::R`](R) reader structure
302impl crate::Readable for MAPRrs {}
303///`write(|w| ..)` method takes [`mapr::W`](W) writer structure
304impl crate::Writable for MAPRrs {
305    type Safety = crate::Unsafe;
306}
307///`reset()` method sets MAPR to value 0
308impl crate::Resettable for MAPRrs {}
stm32f1_staging/stm32f107/afio/mapr.rs

stm32f1_staging/stm32f107/afio/
mapr.rs
