stm32f1_staging/stm32f103/uart4/
cr3.rs

1///Register `CR3` reader
2pub type R = crate::R<CR3rs>;
3///Register `CR3` writer
4pub type W = crate::W<CR3rs>;
5///DMA enable receiver
6pub use crate::stm32f103::usart1::cr3::DMAR;
7///Field `DMAR` reader - DMA enable receiver
8pub use crate::stm32f103::usart1::cr3::DMAR_R;
9///Field `DMAR` writer - DMA enable receiver
10pub use crate::stm32f103::usart1::cr3::DMAR_W;
11///DMA enable transmitter
12pub use crate::stm32f103::usart1::cr3::DMAT;
13///Field `DMAT` reader - DMA enable transmitter
14pub use crate::stm32f103::usart1::cr3::DMAT_R;
15///Field `DMAT` writer - DMA enable transmitter
16pub use crate::stm32f103::usart1::cr3::DMAT_W;
17///Error interrupt enable
18pub use crate::stm32f103::usart1::cr3::EIE;
19///Field `EIE` reader - Error interrupt enable
20pub use crate::stm32f103::usart1::cr3::EIE_R;
21///Field `EIE` writer - Error interrupt enable
22pub use crate::stm32f103::usart1::cr3::EIE_W;
23///Half-duplex selection
24pub use crate::stm32f103::usart1::cr3::HDSEL;
25///Field `HDSEL` reader - Half-duplex selection
26pub use crate::stm32f103::usart1::cr3::HDSEL_R;
27///Field `HDSEL` writer - Half-duplex selection
28pub use crate::stm32f103::usart1::cr3::HDSEL_W;
29///IrDA mode enable
30pub use crate::stm32f103::usart1::cr3::IREN;
31///Field `IREN` reader - IrDA mode enable
32pub use crate::stm32f103::usart1::cr3::IREN_R;
33///Field `IREN` writer - IrDA mode enable
34pub use crate::stm32f103::usart1::cr3::IREN_W;
35///IrDA low-power
36pub use crate::stm32f103::usart1::cr3::IRLP;
37///Field `IRLP` reader - IrDA low-power
38pub use crate::stm32f103::usart1::cr3::IRLP_R;
39///Field `IRLP` writer - IrDA low-power
40pub use crate::stm32f103::usart1::cr3::IRLP_W;
41impl R {
42    ///Bit 0 - Error interrupt enable
43    #[inline(always)]
44    pub fn eie(&self) -> EIE_R {
45        EIE_R::new((self.bits & 1) != 0)
46    }
47    ///Bit 1 - IrDA mode enable
48    #[inline(always)]
49    pub fn iren(&self) -> IREN_R {
50        IREN_R::new(((self.bits >> 1) & 1) != 0)
51    }
52    ///Bit 2 - IrDA low-power
53    #[inline(always)]
54    pub fn irlp(&self) -> IRLP_R {
55        IRLP_R::new(((self.bits >> 2) & 1) != 0)
56    }
57    ///Bit 3 - Half-duplex selection
58    #[inline(always)]
59    pub fn hdsel(&self) -> HDSEL_R {
60        HDSEL_R::new(((self.bits >> 3) & 1) != 0)
61    }
62    ///Bit 6 - DMA enable receiver
63    #[inline(always)]
64    pub fn dmar(&self) -> DMAR_R {
65        DMAR_R::new(((self.bits >> 6) & 1) != 0)
66    }
67    ///Bit 7 - DMA enable transmitter
68    #[inline(always)]
69    pub fn dmat(&self) -> DMAT_R {
70        DMAT_R::new(((self.bits >> 7) & 1) != 0)
71    }
72}
73impl core::fmt::Debug for R {
74    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
75        f.debug_struct("CR3")
76            .field("eie", &self.eie())
77            .field("iren", &self.iren())
78            .field("irlp", &self.irlp())
79            .field("hdsel", &self.hdsel())
80            .field("dmar", &self.dmar())
81            .field("dmat", &self.dmat())
82            .finish()
83    }
84}
85impl W {
86    ///Bit 0 - Error interrupt enable
87    #[inline(always)]
88    pub fn eie(&mut self) -> EIE_W<CR3rs> {
89        EIE_W::new(self, 0)
90    }
91    ///Bit 1 - IrDA mode enable
92    #[inline(always)]
93    pub fn iren(&mut self) -> IREN_W<CR3rs> {
94        IREN_W::new(self, 1)
95    }
96    ///Bit 2 - IrDA low-power
97    #[inline(always)]
98    pub fn irlp(&mut self) -> IRLP_W<CR3rs> {
99        IRLP_W::new(self, 2)
100    }
101    ///Bit 3 - Half-duplex selection
102    #[inline(always)]
103    pub fn hdsel(&mut self) -> HDSEL_W<CR3rs> {
104        HDSEL_W::new(self, 3)
105    }
106    ///Bit 6 - DMA enable receiver
107    #[inline(always)]
108    pub fn dmar(&mut self) -> DMAR_W<CR3rs> {
109        DMAR_W::new(self, 6)
110    }
111    ///Bit 7 - DMA enable transmitter
112    #[inline(always)]
113    pub fn dmat(&mut self) -> DMAT_W<CR3rs> {
114        DMAT_W::new(self, 7)
115    }
116}
117/**UART4_CR3
118
119You can [`read`](crate::Reg::read) this register and get [`cr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
120
121See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#UART4:CR3)*/
122pub struct CR3rs;
123impl crate::RegisterSpec for CR3rs {
124    type Ux = u16;
125}
126///`read()` method returns [`cr3::R`](R) reader structure
127impl crate::Readable for CR3rs {}
128///`write(|w| ..)` method takes [`cr3::W`](W) writer structure
129impl crate::Writable for CR3rs {
130    type Safety = crate::Unsafe;
131}
132///`reset()` method sets CR3 to value 0
133impl crate::Resettable for CR3rs {}
stm32f1_staging/stm32f103/uart4/cr3.rs

stm32f1_staging/stm32f103/uart4/
cr3.rs
