stm32f1_staging/stm32f103/sdio/
clkcr.rs

1///Register `CLKCR` reader
2pub type R = crate::R<CLKCRrs>;
3///Register `CLKCR` writer
4pub type W = crate::W<CLKCRrs>;
5///Field `CLKDIV` reader - Clock divide factor
6pub type CLKDIV_R = crate::FieldReader;
7///Field `CLKDIV` writer - Clock divide factor
8pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9///Field `CLKEN` reader - Clock enable bit
10pub type CLKEN_R = crate::BitReader;
11///Field `CLKEN` writer - Clock enable bit
12pub type CLKEN_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `PWRSAV` reader - Power saving configuration bit
14pub type PWRSAV_R = crate::BitReader;
15///Field `PWRSAV` writer - Power saving configuration bit
16pub type PWRSAV_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `BYPASS` reader - Clock divider bypass enable bit
18pub type BYPASS_R = crate::BitReader;
19///Field `BYPASS` writer - Clock divider bypass enable bit
20pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `WIDBUS` reader - Wide bus mode enable bit
22pub type WIDBUS_R = crate::FieldReader;
23///Field `WIDBUS` writer - Wide bus mode enable bit
24pub type WIDBUS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25///Field `NEGEDGE` reader - SDIO_CK dephasing selection bit
26pub type NEGEDGE_R = crate::BitReader;
27///Field `NEGEDGE` writer - SDIO_CK dephasing selection bit
28pub type NEGEDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `HWFC_EN` reader - HW Flow Control enable
30pub type HWFC_EN_R = crate::BitReader;
31///Field `HWFC_EN` writer - HW Flow Control enable
32pub type HWFC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    ///Bits 0:7 - Clock divide factor
35    #[inline(always)]
36    pub fn clkdiv(&self) -> CLKDIV_R {
37        CLKDIV_R::new((self.bits & 0xff) as u8)
38    }
39    ///Bit 8 - Clock enable bit
40    #[inline(always)]
41    pub fn clken(&self) -> CLKEN_R {
42        CLKEN_R::new(((self.bits >> 8) & 1) != 0)
43    }
44    ///Bit 9 - Power saving configuration bit
45    #[inline(always)]
46    pub fn pwrsav(&self) -> PWRSAV_R {
47        PWRSAV_R::new(((self.bits >> 9) & 1) != 0)
48    }
49    ///Bit 10 - Clock divider bypass enable bit
50    #[inline(always)]
51    pub fn bypass(&self) -> BYPASS_R {
52        BYPASS_R::new(((self.bits >> 10) & 1) != 0)
53    }
54    ///Bits 11:12 - Wide bus mode enable bit
55    #[inline(always)]
56    pub fn widbus(&self) -> WIDBUS_R {
57        WIDBUS_R::new(((self.bits >> 11) & 3) as u8)
58    }
59    ///Bit 13 - SDIO_CK dephasing selection bit
60    #[inline(always)]
61    pub fn negedge(&self) -> NEGEDGE_R {
62        NEGEDGE_R::new(((self.bits >> 13) & 1) != 0)
63    }
64    ///Bit 14 - HW Flow Control enable
65    #[inline(always)]
66    pub fn hwfc_en(&self) -> HWFC_EN_R {
67        HWFC_EN_R::new(((self.bits >> 14) & 1) != 0)
68    }
69}
70impl core::fmt::Debug for R {
71    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
72        f.debug_struct("CLKCR")
73            .field("clkdiv", &self.clkdiv())
74            .field("clken", &self.clken())
75            .field("pwrsav", &self.pwrsav())
76            .field("bypass", &self.bypass())
77            .field("widbus", &self.widbus())
78            .field("negedge", &self.negedge())
79            .field("hwfc_en", &self.hwfc_en())
80            .finish()
81    }
82}
83impl W {
84    ///Bits 0:7 - Clock divide factor
85    #[inline(always)]
86    pub fn clkdiv(&mut self) -> CLKDIV_W<CLKCRrs> {
87        CLKDIV_W::new(self, 0)
88    }
89    ///Bit 8 - Clock enable bit
90    #[inline(always)]
91    pub fn clken(&mut self) -> CLKEN_W<CLKCRrs> {
92        CLKEN_W::new(self, 8)
93    }
94    ///Bit 9 - Power saving configuration bit
95    #[inline(always)]
96    pub fn pwrsav(&mut self) -> PWRSAV_W<CLKCRrs> {
97        PWRSAV_W::new(self, 9)
98    }
99    ///Bit 10 - Clock divider bypass enable bit
100    #[inline(always)]
101    pub fn bypass(&mut self) -> BYPASS_W<CLKCRrs> {
102        BYPASS_W::new(self, 10)
103    }
104    ///Bits 11:12 - Wide bus mode enable bit
105    #[inline(always)]
106    pub fn widbus(&mut self) -> WIDBUS_W<CLKCRrs> {
107        WIDBUS_W::new(self, 11)
108    }
109    ///Bit 13 - SDIO_CK dephasing selection bit
110    #[inline(always)]
111    pub fn negedge(&mut self) -> NEGEDGE_W<CLKCRrs> {
112        NEGEDGE_W::new(self, 13)
113    }
114    ///Bit 14 - HW Flow Control enable
115    #[inline(always)]
116    pub fn hwfc_en(&mut self) -> HWFC_EN_W<CLKCRrs> {
117        HWFC_EN_W::new(self, 14)
118    }
119}
120/**SDI clock control register (SDIO_CLKCR)
121
122You can [`read`](crate::Reg::read) this register and get [`clkcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
123
124See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#SDIO:CLKCR)*/
125pub struct CLKCRrs;
126impl crate::RegisterSpec for CLKCRrs {
127    type Ux = u32;
128}
129///`read()` method returns [`clkcr::R`](R) reader structure
130impl crate::Readable for CLKCRrs {}
131///`write(|w| ..)` method takes [`clkcr::W`](W) writer structure
132impl crate::Writable for CLKCRrs {
133    type Safety = crate::Unsafe;
134}
135///`reset()` method sets CLKCR to value 0
136impl crate::Resettable for CLKCRrs {}
stm32f1_staging/stm32f103/sdio/clkcr.rs

stm32f1_staging/stm32f103/sdio/
clkcr.rs
