stm32f1_staging/stm32f103/rcc/
apb2rstr.rs

1///Register `APB2RSTR` reader
2pub type R = crate::R<APB2RSTRrs>;
3///Register `APB2RSTR` writer
4pub type W = crate::W<APB2RSTRrs>;
5/**Alternate function I/O reset
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum AFIORST {
11    ///1: Reset the selected module
12    Reset = 1,
13}
14impl From<AFIORST> for bool {
15    #[inline(always)]
16    fn from(variant: AFIORST) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `AFIORST` reader - Alternate function I/O reset
21pub type AFIORST_R = crate::BitReader<AFIORST>;
22impl AFIORST_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> Option<AFIORST> {
26        match self.bits {
27            true => Some(AFIORST::Reset),
28            _ => None,
29        }
30    }
31    ///Reset the selected module
32    #[inline(always)]
33    pub fn is_reset(&self) -> bool {
34        *self == AFIORST::Reset
35    }
36}
37///Field `AFIORST` writer - Alternate function I/O reset
38pub type AFIORST_W<'a, REG> = crate::BitWriter<'a, REG, AFIORST>;
39impl<'a, REG> AFIORST_W<'a, REG>
40where
41    REG: crate::Writable + crate::RegisterSpec,
42{
43    ///Reset the selected module
44    #[inline(always)]
45    pub fn reset(self) -> &'a mut crate::W<REG> {
46        self.variant(AFIORST::Reset)
47    }
48}
49///Field `IOPARST` reader - IO port A reset
50pub use AFIORST_R as IOPARST_R;
51///Field `IOPBRST` reader - IO port B reset
52pub use AFIORST_R as IOPBRST_R;
53///Field `IOPCRST` reader - IO port C reset
54pub use AFIORST_R as IOPCRST_R;
55///Field `IOPDRST` reader - IO port D reset
56pub use AFIORST_R as IOPDRST_R;
57///Field `IOPERST` reader - IO port E reset
58pub use AFIORST_R as IOPERST_R;
59///Field `IOPFRST` reader - IO port F reset
60pub use AFIORST_R as IOPFRST_R;
61///Field `IOPGRST` reader - IO port G reset
62pub use AFIORST_R as IOPGRST_R;
63///Field `ADC1RST` reader - ADC 1 interface reset
64pub use AFIORST_R as ADC1RST_R;
65///Field `ADC2RST` reader - ADC 2 interface reset
66pub use AFIORST_R as ADC2RST_R;
67///Field `TIM1RST` reader - TIM1 timer reset
68pub use AFIORST_R as TIM1RST_R;
69///Field `SPI1RST` reader - SPI 1 reset
70pub use AFIORST_R as SPI1RST_R;
71///Field `TIM8RST` reader - TIM8 timer reset
72pub use AFIORST_R as TIM8RST_R;
73///Field `USART1RST` reader - USART1 reset
74pub use AFIORST_R as USART1RST_R;
75///Field `ADC3RST` reader - ADC 3 interface reset
76pub use AFIORST_R as ADC3RST_R;
77///Field `TIM9RST` reader - TIM9 timer reset
78pub use AFIORST_R as TIM9RST_R;
79///Field `TIM10RST` reader - TIM10 timer reset
80pub use AFIORST_R as TIM10RST_R;
81///Field `TIM11RST` reader - TIM11 timer reset
82pub use AFIORST_R as TIM11RST_R;
83///Field `IOPARST` writer - IO port A reset
84pub use AFIORST_W as IOPARST_W;
85///Field `IOPBRST` writer - IO port B reset
86pub use AFIORST_W as IOPBRST_W;
87///Field `IOPCRST` writer - IO port C reset
88pub use AFIORST_W as IOPCRST_W;
89///Field `IOPDRST` writer - IO port D reset
90pub use AFIORST_W as IOPDRST_W;
91///Field `IOPERST` writer - IO port E reset
92pub use AFIORST_W as IOPERST_W;
93///Field `IOPFRST` writer - IO port F reset
94pub use AFIORST_W as IOPFRST_W;
95///Field `IOPGRST` writer - IO port G reset
96pub use AFIORST_W as IOPGRST_W;
97///Field `ADC1RST` writer - ADC 1 interface reset
98pub use AFIORST_W as ADC1RST_W;
99///Field `ADC2RST` writer - ADC 2 interface reset
100pub use AFIORST_W as ADC2RST_W;
101///Field `TIM1RST` writer - TIM1 timer reset
102pub use AFIORST_W as TIM1RST_W;
103///Field `SPI1RST` writer - SPI 1 reset
104pub use AFIORST_W as SPI1RST_W;
105///Field `TIM8RST` writer - TIM8 timer reset
106pub use AFIORST_W as TIM8RST_W;
107///Field `USART1RST` writer - USART1 reset
108pub use AFIORST_W as USART1RST_W;
109///Field `ADC3RST` writer - ADC 3 interface reset
110pub use AFIORST_W as ADC3RST_W;
111///Field `TIM9RST` writer - TIM9 timer reset
112pub use AFIORST_W as TIM9RST_W;
113///Field `TIM10RST` writer - TIM10 timer reset
114pub use AFIORST_W as TIM10RST_W;
115///Field `TIM11RST` writer - TIM11 timer reset
116pub use AFIORST_W as TIM11RST_W;
117impl R {
118    ///Bit 0 - Alternate function I/O reset
119    #[inline(always)]
120    pub fn afiorst(&self) -> AFIORST_R {
121        AFIORST_R::new((self.bits & 1) != 0)
122    }
123    ///Bit 2 - IO port A reset
124    #[inline(always)]
125    pub fn ioparst(&self) -> IOPARST_R {
126        IOPARST_R::new(((self.bits >> 2) & 1) != 0)
127    }
128    ///Bit 3 - IO port B reset
129    #[inline(always)]
130    pub fn iopbrst(&self) -> IOPBRST_R {
131        IOPBRST_R::new(((self.bits >> 3) & 1) != 0)
132    }
133    ///Bit 4 - IO port C reset
134    #[inline(always)]
135    pub fn iopcrst(&self) -> IOPCRST_R {
136        IOPCRST_R::new(((self.bits >> 4) & 1) != 0)
137    }
138    ///Bit 5 - IO port D reset
139    #[inline(always)]
140    pub fn iopdrst(&self) -> IOPDRST_R {
141        IOPDRST_R::new(((self.bits >> 5) & 1) != 0)
142    }
143    ///Bit 6 - IO port E reset
144    #[inline(always)]
145    pub fn ioperst(&self) -> IOPERST_R {
146        IOPERST_R::new(((self.bits >> 6) & 1) != 0)
147    }
148    ///Bit 7 - IO port F reset
149    #[inline(always)]
150    pub fn iopfrst(&self) -> IOPFRST_R {
151        IOPFRST_R::new(((self.bits >> 7) & 1) != 0)
152    }
153    ///Bit 8 - IO port G reset
154    #[inline(always)]
155    pub fn iopgrst(&self) -> IOPGRST_R {
156        IOPGRST_R::new(((self.bits >> 8) & 1) != 0)
157    }
158    ///Bit 9 - ADC 1 interface reset
159    #[inline(always)]
160    pub fn adc1rst(&self) -> ADC1RST_R {
161        ADC1RST_R::new(((self.bits >> 9) & 1) != 0)
162    }
163    ///Bit 10 - ADC 2 interface reset
164    #[inline(always)]
165    pub fn adc2rst(&self) -> ADC2RST_R {
166        ADC2RST_R::new(((self.bits >> 10) & 1) != 0)
167    }
168    ///Bit 11 - TIM1 timer reset
169    #[inline(always)]
170    pub fn tim1rst(&self) -> TIM1RST_R {
171        TIM1RST_R::new(((self.bits >> 11) & 1) != 0)
172    }
173    ///Bit 12 - SPI 1 reset
174    #[inline(always)]
175    pub fn spi1rst(&self) -> SPI1RST_R {
176        SPI1RST_R::new(((self.bits >> 12) & 1) != 0)
177    }
178    ///Bit 13 - TIM8 timer reset
179    #[inline(always)]
180    pub fn tim8rst(&self) -> TIM8RST_R {
181        TIM8RST_R::new(((self.bits >> 13) & 1) != 0)
182    }
183    ///Bit 14 - USART1 reset
184    #[inline(always)]
185    pub fn usart1rst(&self) -> USART1RST_R {
186        USART1RST_R::new(((self.bits >> 14) & 1) != 0)
187    }
188    ///Bit 15 - ADC 3 interface reset
189    #[inline(always)]
190    pub fn adc3rst(&self) -> ADC3RST_R {
191        ADC3RST_R::new(((self.bits >> 15) & 1) != 0)
192    }
193    ///Bit 19 - TIM9 timer reset
194    #[inline(always)]
195    pub fn tim9rst(&self) -> TIM9RST_R {
196        TIM9RST_R::new(((self.bits >> 19) & 1) != 0)
197    }
198    ///Bit 20 - TIM10 timer reset
199    #[inline(always)]
200    pub fn tim10rst(&self) -> TIM10RST_R {
201        TIM10RST_R::new(((self.bits >> 20) & 1) != 0)
202    }
203    ///Bit 21 - TIM11 timer reset
204    #[inline(always)]
205    pub fn tim11rst(&self) -> TIM11RST_R {
206        TIM11RST_R::new(((self.bits >> 21) & 1) != 0)
207    }
208}
209impl core::fmt::Debug for R {
210    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
211        f.debug_struct("APB2RSTR")
212            .field("afiorst", &self.afiorst())
213            .field("ioparst", &self.ioparst())
214            .field("iopbrst", &self.iopbrst())
215            .field("iopcrst", &self.iopcrst())
216            .field("iopdrst", &self.iopdrst())
217            .field("ioperst", &self.ioperst())
218            .field("iopfrst", &self.iopfrst())
219            .field("iopgrst", &self.iopgrst())
220            .field("adc1rst", &self.adc1rst())
221            .field("adc2rst", &self.adc2rst())
222            .field("tim1rst", &self.tim1rst())
223            .field("spi1rst", &self.spi1rst())
224            .field("tim8rst", &self.tim8rst())
225            .field("usart1rst", &self.usart1rst())
226            .field("adc3rst", &self.adc3rst())
227            .field("tim9rst", &self.tim9rst())
228            .field("tim10rst", &self.tim10rst())
229            .field("tim11rst", &self.tim11rst())
230            .finish()
231    }
232}
233impl W {
234    ///Bit 0 - Alternate function I/O reset
235    #[inline(always)]
236    pub fn afiorst(&mut self) -> AFIORST_W<APB2RSTRrs> {
237        AFIORST_W::new(self, 0)
238    }
239    ///Bit 2 - IO port A reset
240    #[inline(always)]
241    pub fn ioparst(&mut self) -> IOPARST_W<APB2RSTRrs> {
242        IOPARST_W::new(self, 2)
243    }
244    ///Bit 3 - IO port B reset
245    #[inline(always)]
246    pub fn iopbrst(&mut self) -> IOPBRST_W<APB2RSTRrs> {
247        IOPBRST_W::new(self, 3)
248    }
249    ///Bit 4 - IO port C reset
250    #[inline(always)]
251    pub fn iopcrst(&mut self) -> IOPCRST_W<APB2RSTRrs> {
252        IOPCRST_W::new(self, 4)
253    }
254    ///Bit 5 - IO port D reset
255    #[inline(always)]
256    pub fn iopdrst(&mut self) -> IOPDRST_W<APB2RSTRrs> {
257        IOPDRST_W::new(self, 5)
258    }
259    ///Bit 6 - IO port E reset
260    #[inline(always)]
261    pub fn ioperst(&mut self) -> IOPERST_W<APB2RSTRrs> {
262        IOPERST_W::new(self, 6)
263    }
264    ///Bit 7 - IO port F reset
265    #[inline(always)]
266    pub fn iopfrst(&mut self) -> IOPFRST_W<APB2RSTRrs> {
267        IOPFRST_W::new(self, 7)
268    }
269    ///Bit 8 - IO port G reset
270    #[inline(always)]
271    pub fn iopgrst(&mut self) -> IOPGRST_W<APB2RSTRrs> {
272        IOPGRST_W::new(self, 8)
273    }
274    ///Bit 9 - ADC 1 interface reset
275    #[inline(always)]
276    pub fn adc1rst(&mut self) -> ADC1RST_W<APB2RSTRrs> {
277        ADC1RST_W::new(self, 9)
278    }
279    ///Bit 10 - ADC 2 interface reset
280    #[inline(always)]
281    pub fn adc2rst(&mut self) -> ADC2RST_W<APB2RSTRrs> {
282        ADC2RST_W::new(self, 10)
283    }
284    ///Bit 11 - TIM1 timer reset
285    #[inline(always)]
286    pub fn tim1rst(&mut self) -> TIM1RST_W<APB2RSTRrs> {
287        TIM1RST_W::new(self, 11)
288    }
289    ///Bit 12 - SPI 1 reset
290    #[inline(always)]
291    pub fn spi1rst(&mut self) -> SPI1RST_W<APB2RSTRrs> {
292        SPI1RST_W::new(self, 12)
293    }
294    ///Bit 13 - TIM8 timer reset
295    #[inline(always)]
296    pub fn tim8rst(&mut self) -> TIM8RST_W<APB2RSTRrs> {
297        TIM8RST_W::new(self, 13)
298    }
299    ///Bit 14 - USART1 reset
300    #[inline(always)]
301    pub fn usart1rst(&mut self) -> USART1RST_W<APB2RSTRrs> {
302        USART1RST_W::new(self, 14)
303    }
304    ///Bit 15 - ADC 3 interface reset
305    #[inline(always)]
306    pub fn adc3rst(&mut self) -> ADC3RST_W<APB2RSTRrs> {
307        ADC3RST_W::new(self, 15)
308    }
309    ///Bit 19 - TIM9 timer reset
310    #[inline(always)]
311    pub fn tim9rst(&mut self) -> TIM9RST_W<APB2RSTRrs> {
312        TIM9RST_W::new(self, 19)
313    }
314    ///Bit 20 - TIM10 timer reset
315    #[inline(always)]
316    pub fn tim10rst(&mut self) -> TIM10RST_W<APB2RSTRrs> {
317        TIM10RST_W::new(self, 20)
318    }
319    ///Bit 21 - TIM11 timer reset
320    #[inline(always)]
321    pub fn tim11rst(&mut self) -> TIM11RST_W<APB2RSTRrs> {
322        TIM11RST_W::new(self, 21)
323    }
324}
325/**APB2 peripheral reset register (RCC_APB2RSTR)
326
327You can [`read`](crate::Reg::read) this register and get [`apb2rstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2rstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
328
329See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:APB2RSTR)*/
330pub struct APB2RSTRrs;
331impl crate::RegisterSpec for APB2RSTRrs {
332    type Ux = u32;
333}
334///`read()` method returns [`apb2rstr::R`](R) reader structure
335impl crate::Readable for APB2RSTRrs {}
336///`write(|w| ..)` method takes [`apb2rstr::W`](W) writer structure
337impl crate::Writable for APB2RSTRrs {
338    type Safety = crate::Unsafe;
339}
340///`reset()` method sets APB2RSTR to value 0
341impl crate::Resettable for APB2RSTRrs {}
stm32f1_staging/stm32f103/rcc/apb2rstr.rs

stm32f1_staging/stm32f103/rcc/
apb2rstr.rs
