stm32f1_staging/stm32f103/rcc/
apb2enr.rs

1///Register `APB2ENR` reader
2pub type R = crate::R<APB2ENRrs>;
3///Register `APB2ENR` writer
4pub type W = crate::W<APB2ENRrs>;
5/**Alternate function I/O clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum AFIOEN {
11    ///0: The selected clock is disabled
12    Disabled = 0,
13    ///1: The selected clock is enabled
14    Enabled = 1,
15}
16impl From<AFIOEN> for bool {
17    #[inline(always)]
18    fn from(variant: AFIOEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `AFIOEN` reader - Alternate function I/O clock enable
23pub type AFIOEN_R = crate::BitReader<AFIOEN>;
24impl AFIOEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> AFIOEN {
28        match self.bits {
29            false => AFIOEN::Disabled,
30            true => AFIOEN::Enabled,
31        }
32    }
33    ///The selected clock is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == AFIOEN::Disabled
37    }
38    ///The selected clock is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == AFIOEN::Enabled
42    }
43}
44///Field `AFIOEN` writer - Alternate function I/O clock enable
45pub type AFIOEN_W<'a, REG> = crate::BitWriter<'a, REG, AFIOEN>;
46impl<'a, REG> AFIOEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The selected clock is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(AFIOEN::Disabled)
54    }
55    ///The selected clock is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(AFIOEN::Enabled)
59    }
60}
61///Field `IOPAEN` reader - I/O port A clock enable
62pub use AFIOEN_R as IOPAEN_R;
63///Field `IOPBEN` reader - I/O port B clock enable
64pub use AFIOEN_R as IOPBEN_R;
65///Field `IOPCEN` reader - I/O port C clock enable
66pub use AFIOEN_R as IOPCEN_R;
67///Field `IOPDEN` reader - I/O port D clock enable
68pub use AFIOEN_R as IOPDEN_R;
69///Field `IOPEEN` reader - I/O port E clock enable
70pub use AFIOEN_R as IOPEEN_R;
71///Field `IOPFEN` reader - I/O port F clock enable
72pub use AFIOEN_R as IOPFEN_R;
73///Field `IOPGEN` reader - I/O port G clock enable
74pub use AFIOEN_R as IOPGEN_R;
75///Field `ADC1EN` reader - ADC 1 interface clock enable
76pub use AFIOEN_R as ADC1EN_R;
77///Field `ADC2EN` reader - ADC 2 interface clock enable
78pub use AFIOEN_R as ADC2EN_R;
79///Field `TIM1EN` reader - TIM1 Timer clock enable
80pub use AFIOEN_R as TIM1EN_R;
81///Field `SPI1EN` reader - SPI 1 clock enable
82pub use AFIOEN_R as SPI1EN_R;
83///Field `TIM8EN` reader - TIM8 Timer clock enable
84pub use AFIOEN_R as TIM8EN_R;
85///Field `USART1EN` reader - USART1 clock enable
86pub use AFIOEN_R as USART1EN_R;
87///Field `ADC3EN` reader - ADC3 interface clock enable
88pub use AFIOEN_R as ADC3EN_R;
89///Field `TIM9EN` reader - TIM9 Timer clock enable
90pub use AFIOEN_R as TIM9EN_R;
91///Field `TIM10EN` reader - TIM10 Timer clock enable
92pub use AFIOEN_R as TIM10EN_R;
93///Field `TIM11EN` reader - TIM11 Timer clock enable
94pub use AFIOEN_R as TIM11EN_R;
95///Field `IOPAEN` writer - I/O port A clock enable
96pub use AFIOEN_W as IOPAEN_W;
97///Field `IOPBEN` writer - I/O port B clock enable
98pub use AFIOEN_W as IOPBEN_W;
99///Field `IOPCEN` writer - I/O port C clock enable
100pub use AFIOEN_W as IOPCEN_W;
101///Field `IOPDEN` writer - I/O port D clock enable
102pub use AFIOEN_W as IOPDEN_W;
103///Field `IOPEEN` writer - I/O port E clock enable
104pub use AFIOEN_W as IOPEEN_W;
105///Field `IOPFEN` writer - I/O port F clock enable
106pub use AFIOEN_W as IOPFEN_W;
107///Field `IOPGEN` writer - I/O port G clock enable
108pub use AFIOEN_W as IOPGEN_W;
109///Field `ADC1EN` writer - ADC 1 interface clock enable
110pub use AFIOEN_W as ADC1EN_W;
111///Field `ADC2EN` writer - ADC 2 interface clock enable
112pub use AFIOEN_W as ADC2EN_W;
113///Field `TIM1EN` writer - TIM1 Timer clock enable
114pub use AFIOEN_W as TIM1EN_W;
115///Field `SPI1EN` writer - SPI 1 clock enable
116pub use AFIOEN_W as SPI1EN_W;
117///Field `TIM8EN` writer - TIM8 Timer clock enable
118pub use AFIOEN_W as TIM8EN_W;
119///Field `USART1EN` writer - USART1 clock enable
120pub use AFIOEN_W as USART1EN_W;
121///Field `ADC3EN` writer - ADC3 interface clock enable
122pub use AFIOEN_W as ADC3EN_W;
123///Field `TIM9EN` writer - TIM9 Timer clock enable
124pub use AFIOEN_W as TIM9EN_W;
125///Field `TIM10EN` writer - TIM10 Timer clock enable
126pub use AFIOEN_W as TIM10EN_W;
127///Field `TIM11EN` writer - TIM11 Timer clock enable
128pub use AFIOEN_W as TIM11EN_W;
129impl R {
130    ///Bit 0 - Alternate function I/O clock enable
131    #[inline(always)]
132    pub fn afioen(&self) -> AFIOEN_R {
133        AFIOEN_R::new((self.bits & 1) != 0)
134    }
135    ///Bit 2 - I/O port A clock enable
136    #[inline(always)]
137    pub fn iopaen(&self) -> IOPAEN_R {
138        IOPAEN_R::new(((self.bits >> 2) & 1) != 0)
139    }
140    ///Bit 3 - I/O port B clock enable
141    #[inline(always)]
142    pub fn iopben(&self) -> IOPBEN_R {
143        IOPBEN_R::new(((self.bits >> 3) & 1) != 0)
144    }
145    ///Bit 4 - I/O port C clock enable
146    #[inline(always)]
147    pub fn iopcen(&self) -> IOPCEN_R {
148        IOPCEN_R::new(((self.bits >> 4) & 1) != 0)
149    }
150    ///Bit 5 - I/O port D clock enable
151    #[inline(always)]
152    pub fn iopden(&self) -> IOPDEN_R {
153        IOPDEN_R::new(((self.bits >> 5) & 1) != 0)
154    }
155    ///Bit 6 - I/O port E clock enable
156    #[inline(always)]
157    pub fn iopeen(&self) -> IOPEEN_R {
158        IOPEEN_R::new(((self.bits >> 6) & 1) != 0)
159    }
160    ///Bit 7 - I/O port F clock enable
161    #[inline(always)]
162    pub fn iopfen(&self) -> IOPFEN_R {
163        IOPFEN_R::new(((self.bits >> 7) & 1) != 0)
164    }
165    ///Bit 8 - I/O port G clock enable
166    #[inline(always)]
167    pub fn iopgen(&self) -> IOPGEN_R {
168        IOPGEN_R::new(((self.bits >> 8) & 1) != 0)
169    }
170    ///Bit 9 - ADC 1 interface clock enable
171    #[inline(always)]
172    pub fn adc1en(&self) -> ADC1EN_R {
173        ADC1EN_R::new(((self.bits >> 9) & 1) != 0)
174    }
175    ///Bit 10 - ADC 2 interface clock enable
176    #[inline(always)]
177    pub fn adc2en(&self) -> ADC2EN_R {
178        ADC2EN_R::new(((self.bits >> 10) & 1) != 0)
179    }
180    ///Bit 11 - TIM1 Timer clock enable
181    #[inline(always)]
182    pub fn tim1en(&self) -> TIM1EN_R {
183        TIM1EN_R::new(((self.bits >> 11) & 1) != 0)
184    }
185    ///Bit 12 - SPI 1 clock enable
186    #[inline(always)]
187    pub fn spi1en(&self) -> SPI1EN_R {
188        SPI1EN_R::new(((self.bits >> 12) & 1) != 0)
189    }
190    ///Bit 13 - TIM8 Timer clock enable
191    #[inline(always)]
192    pub fn tim8en(&self) -> TIM8EN_R {
193        TIM8EN_R::new(((self.bits >> 13) & 1) != 0)
194    }
195    ///Bit 14 - USART1 clock enable
196    #[inline(always)]
197    pub fn usart1en(&self) -> USART1EN_R {
198        USART1EN_R::new(((self.bits >> 14) & 1) != 0)
199    }
200    ///Bit 15 - ADC3 interface clock enable
201    #[inline(always)]
202    pub fn adc3en(&self) -> ADC3EN_R {
203        ADC3EN_R::new(((self.bits >> 15) & 1) != 0)
204    }
205    ///Bit 19 - TIM9 Timer clock enable
206    #[inline(always)]
207    pub fn tim9en(&self) -> TIM9EN_R {
208        TIM9EN_R::new(((self.bits >> 19) & 1) != 0)
209    }
210    ///Bit 20 - TIM10 Timer clock enable
211    #[inline(always)]
212    pub fn tim10en(&self) -> TIM10EN_R {
213        TIM10EN_R::new(((self.bits >> 20) & 1) != 0)
214    }
215    ///Bit 21 - TIM11 Timer clock enable
216    #[inline(always)]
217    pub fn tim11en(&self) -> TIM11EN_R {
218        TIM11EN_R::new(((self.bits >> 21) & 1) != 0)
219    }
220}
221impl core::fmt::Debug for R {
222    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
223        f.debug_struct("APB2ENR")
224            .field("afioen", &self.afioen())
225            .field("iopaen", &self.iopaen())
226            .field("iopben", &self.iopben())
227            .field("iopcen", &self.iopcen())
228            .field("iopden", &self.iopden())
229            .field("iopeen", &self.iopeen())
230            .field("iopfen", &self.iopfen())
231            .field("iopgen", &self.iopgen())
232            .field("adc1en", &self.adc1en())
233            .field("adc2en", &self.adc2en())
234            .field("tim1en", &self.tim1en())
235            .field("spi1en", &self.spi1en())
236            .field("tim8en", &self.tim8en())
237            .field("usart1en", &self.usart1en())
238            .field("adc3en", &self.adc3en())
239            .field("tim9en", &self.tim9en())
240            .field("tim10en", &self.tim10en())
241            .field("tim11en", &self.tim11en())
242            .finish()
243    }
244}
245impl W {
246    ///Bit 0 - Alternate function I/O clock enable
247    #[inline(always)]
248    pub fn afioen(&mut self) -> AFIOEN_W<APB2ENRrs> {
249        AFIOEN_W::new(self, 0)
250    }
251    ///Bit 2 - I/O port A clock enable
252    #[inline(always)]
253    pub fn iopaen(&mut self) -> IOPAEN_W<APB2ENRrs> {
254        IOPAEN_W::new(self, 2)
255    }
256    ///Bit 3 - I/O port B clock enable
257    #[inline(always)]
258    pub fn iopben(&mut self) -> IOPBEN_W<APB2ENRrs> {
259        IOPBEN_W::new(self, 3)
260    }
261    ///Bit 4 - I/O port C clock enable
262    #[inline(always)]
263    pub fn iopcen(&mut self) -> IOPCEN_W<APB2ENRrs> {
264        IOPCEN_W::new(self, 4)
265    }
266    ///Bit 5 - I/O port D clock enable
267    #[inline(always)]
268    pub fn iopden(&mut self) -> IOPDEN_W<APB2ENRrs> {
269        IOPDEN_W::new(self, 5)
270    }
271    ///Bit 6 - I/O port E clock enable
272    #[inline(always)]
273    pub fn iopeen(&mut self) -> IOPEEN_W<APB2ENRrs> {
274        IOPEEN_W::new(self, 6)
275    }
276    ///Bit 7 - I/O port F clock enable
277    #[inline(always)]
278    pub fn iopfen(&mut self) -> IOPFEN_W<APB2ENRrs> {
279        IOPFEN_W::new(self, 7)
280    }
281    ///Bit 8 - I/O port G clock enable
282    #[inline(always)]
283    pub fn iopgen(&mut self) -> IOPGEN_W<APB2ENRrs> {
284        IOPGEN_W::new(self, 8)
285    }
286    ///Bit 9 - ADC 1 interface clock enable
287    #[inline(always)]
288    pub fn adc1en(&mut self) -> ADC1EN_W<APB2ENRrs> {
289        ADC1EN_W::new(self, 9)
290    }
291    ///Bit 10 - ADC 2 interface clock enable
292    #[inline(always)]
293    pub fn adc2en(&mut self) -> ADC2EN_W<APB2ENRrs> {
294        ADC2EN_W::new(self, 10)
295    }
296    ///Bit 11 - TIM1 Timer clock enable
297    #[inline(always)]
298    pub fn tim1en(&mut self) -> TIM1EN_W<APB2ENRrs> {
299        TIM1EN_W::new(self, 11)
300    }
301    ///Bit 12 - SPI 1 clock enable
302    #[inline(always)]
303    pub fn spi1en(&mut self) -> SPI1EN_W<APB2ENRrs> {
304        SPI1EN_W::new(self, 12)
305    }
306    ///Bit 13 - TIM8 Timer clock enable
307    #[inline(always)]
308    pub fn tim8en(&mut self) -> TIM8EN_W<APB2ENRrs> {
309        TIM8EN_W::new(self, 13)
310    }
311    ///Bit 14 - USART1 clock enable
312    #[inline(always)]
313    pub fn usart1en(&mut self) -> USART1EN_W<APB2ENRrs> {
314        USART1EN_W::new(self, 14)
315    }
316    ///Bit 15 - ADC3 interface clock enable
317    #[inline(always)]
318    pub fn adc3en(&mut self) -> ADC3EN_W<APB2ENRrs> {
319        ADC3EN_W::new(self, 15)
320    }
321    ///Bit 19 - TIM9 Timer clock enable
322    #[inline(always)]
323    pub fn tim9en(&mut self) -> TIM9EN_W<APB2ENRrs> {
324        TIM9EN_W::new(self, 19)
325    }
326    ///Bit 20 - TIM10 Timer clock enable
327    #[inline(always)]
328    pub fn tim10en(&mut self) -> TIM10EN_W<APB2ENRrs> {
329        TIM10EN_W::new(self, 20)
330    }
331    ///Bit 21 - TIM11 Timer clock enable
332    #[inline(always)]
333    pub fn tim11en(&mut self) -> TIM11EN_W<APB2ENRrs> {
334        TIM11EN_W::new(self, 21)
335    }
336}
337/**APB2 peripheral clock enable register (RCC_APB2ENR)
338
339You can [`read`](crate::Reg::read) this register and get [`apb2enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
340
341See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:APB2ENR)*/
342pub struct APB2ENRrs;
343impl crate::RegisterSpec for APB2ENRrs {
344    type Ux = u32;
345}
346///`read()` method returns [`apb2enr::R`](R) reader structure
347impl crate::Readable for APB2ENRrs {}
348///`write(|w| ..)` method takes [`apb2enr::W`](W) writer structure
349impl crate::Writable for APB2ENRrs {
350    type Safety = crate::Unsafe;
351}
352///`reset()` method sets APB2ENR to value 0
353impl crate::Resettable for APB2ENRrs {}
stm32f1_staging/stm32f103/rcc/apb2enr.rs

stm32f1_staging/stm32f103/rcc/
apb2enr.rs
