stm32f1_staging/stm32f103/rcc/
apb1enr.rs

1///Register `APB1ENR` reader
2pub type R = crate::R<APB1ENRrs>;
3///Register `APB1ENR` writer
4pub type W = crate::W<APB1ENRrs>;
5/**Timer 2 clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum TIM2EN {
11    ///0: The selected clock is disabled
12    Disabled = 0,
13    ///1: The selected clock is enabled
14    Enabled = 1,
15}
16impl From<TIM2EN> for bool {
17    #[inline(always)]
18    fn from(variant: TIM2EN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `TIM2EN` reader - Timer 2 clock enable
23pub type TIM2EN_R = crate::BitReader<TIM2EN>;
24impl TIM2EN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> TIM2EN {
28        match self.bits {
29            false => TIM2EN::Disabled,
30            true => TIM2EN::Enabled,
31        }
32    }
33    ///The selected clock is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == TIM2EN::Disabled
37    }
38    ///The selected clock is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == TIM2EN::Enabled
42    }
43}
44///Field `TIM2EN` writer - Timer 2 clock enable
45pub type TIM2EN_W<'a, REG> = crate::BitWriter<'a, REG, TIM2EN>;
46impl<'a, REG> TIM2EN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The selected clock is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(TIM2EN::Disabled)
54    }
55    ///The selected clock is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(TIM2EN::Enabled)
59    }
60}
61///Field `TIM3EN` reader - Timer 3 clock enable
62pub use TIM2EN_R as TIM3EN_R;
63///Field `TIM4EN` reader - Timer 4 clock enable
64pub use TIM2EN_R as TIM4EN_R;
65///Field `TIM5EN` reader - Timer 5 clock enable
66pub use TIM2EN_R as TIM5EN_R;
67///Field `TIM6EN` reader - Timer 6 clock enable
68pub use TIM2EN_R as TIM6EN_R;
69///Field `TIM7EN` reader - Timer 7 clock enable
70pub use TIM2EN_R as TIM7EN_R;
71///Field `TIM12EN` reader - Timer 12 clock enable
72pub use TIM2EN_R as TIM12EN_R;
73///Field `TIM13EN` reader - Timer 13 clock enable
74pub use TIM2EN_R as TIM13EN_R;
75///Field `TIM14EN` reader - Timer 14 clock enable
76pub use TIM2EN_R as TIM14EN_R;
77///Field `WWDGEN` reader - Window watchdog clock enable
78pub use TIM2EN_R as WWDGEN_R;
79///Field `SPI2EN` reader - SPI 2 clock enable
80pub use TIM2EN_R as SPI2EN_R;
81///Field `SPI3EN` reader - SPI 3 clock enable
82pub use TIM2EN_R as SPI3EN_R;
83///Field `USART2EN` reader - USART 2 clock enable
84pub use TIM2EN_R as USART2EN_R;
85///Field `USART3EN` reader - USART 3 clock enable
86pub use TIM2EN_R as USART3EN_R;
87///Field `UART4EN` reader - UART 4 clock enable
88pub use TIM2EN_R as UART4EN_R;
89///Field `UART5EN` reader - UART 5 clock enable
90pub use TIM2EN_R as UART5EN_R;
91///Field `I2C1EN` reader - I2C 1 clock enable
92pub use TIM2EN_R as I2C1EN_R;
93///Field `I2C2EN` reader - I2C 2 clock enable
94pub use TIM2EN_R as I2C2EN_R;
95///Field `USBEN` reader - USB clock enable
96pub use TIM2EN_R as USBEN_R;
97///Field `CANEN` reader - CAN clock enable
98pub use TIM2EN_R as CANEN_R;
99///Field `BKPEN` reader - Backup interface clock enable
100pub use TIM2EN_R as BKPEN_R;
101///Field `PWREN` reader - Power interface clock enable
102pub use TIM2EN_R as PWREN_R;
103///Field `DACEN` reader - DAC interface clock enable
104pub use TIM2EN_R as DACEN_R;
105///Field `TIM3EN` writer - Timer 3 clock enable
106pub use TIM2EN_W as TIM3EN_W;
107///Field `TIM4EN` writer - Timer 4 clock enable
108pub use TIM2EN_W as TIM4EN_W;
109///Field `TIM5EN` writer - Timer 5 clock enable
110pub use TIM2EN_W as TIM5EN_W;
111///Field `TIM6EN` writer - Timer 6 clock enable
112pub use TIM2EN_W as TIM6EN_W;
113///Field `TIM7EN` writer - Timer 7 clock enable
114pub use TIM2EN_W as TIM7EN_W;
115///Field `TIM12EN` writer - Timer 12 clock enable
116pub use TIM2EN_W as TIM12EN_W;
117///Field `TIM13EN` writer - Timer 13 clock enable
118pub use TIM2EN_W as TIM13EN_W;
119///Field `TIM14EN` writer - Timer 14 clock enable
120pub use TIM2EN_W as TIM14EN_W;
121///Field `WWDGEN` writer - Window watchdog clock enable
122pub use TIM2EN_W as WWDGEN_W;
123///Field `SPI2EN` writer - SPI 2 clock enable
124pub use TIM2EN_W as SPI2EN_W;
125///Field `SPI3EN` writer - SPI 3 clock enable
126pub use TIM2EN_W as SPI3EN_W;
127///Field `USART2EN` writer - USART 2 clock enable
128pub use TIM2EN_W as USART2EN_W;
129///Field `USART3EN` writer - USART 3 clock enable
130pub use TIM2EN_W as USART3EN_W;
131///Field `UART4EN` writer - UART 4 clock enable
132pub use TIM2EN_W as UART4EN_W;
133///Field `UART5EN` writer - UART 5 clock enable
134pub use TIM2EN_W as UART5EN_W;
135///Field `I2C1EN` writer - I2C 1 clock enable
136pub use TIM2EN_W as I2C1EN_W;
137///Field `I2C2EN` writer - I2C 2 clock enable
138pub use TIM2EN_W as I2C2EN_W;
139///Field `USBEN` writer - USB clock enable
140pub use TIM2EN_W as USBEN_W;
141///Field `CANEN` writer - CAN clock enable
142pub use TIM2EN_W as CANEN_W;
143///Field `BKPEN` writer - Backup interface clock enable
144pub use TIM2EN_W as BKPEN_W;
145///Field `PWREN` writer - Power interface clock enable
146pub use TIM2EN_W as PWREN_W;
147///Field `DACEN` writer - DAC interface clock enable
148pub use TIM2EN_W as DACEN_W;
149impl R {
150    ///Bit 0 - Timer 2 clock enable
151    #[inline(always)]
152    pub fn tim2en(&self) -> TIM2EN_R {
153        TIM2EN_R::new((self.bits & 1) != 0)
154    }
155    ///Bit 1 - Timer 3 clock enable
156    #[inline(always)]
157    pub fn tim3en(&self) -> TIM3EN_R {
158        TIM3EN_R::new(((self.bits >> 1) & 1) != 0)
159    }
160    ///Bit 2 - Timer 4 clock enable
161    #[inline(always)]
162    pub fn tim4en(&self) -> TIM4EN_R {
163        TIM4EN_R::new(((self.bits >> 2) & 1) != 0)
164    }
165    ///Bit 3 - Timer 5 clock enable
166    #[inline(always)]
167    pub fn tim5en(&self) -> TIM5EN_R {
168        TIM5EN_R::new(((self.bits >> 3) & 1) != 0)
169    }
170    ///Bit 4 - Timer 6 clock enable
171    #[inline(always)]
172    pub fn tim6en(&self) -> TIM6EN_R {
173        TIM6EN_R::new(((self.bits >> 4) & 1) != 0)
174    }
175    ///Bit 5 - Timer 7 clock enable
176    #[inline(always)]
177    pub fn tim7en(&self) -> TIM7EN_R {
178        TIM7EN_R::new(((self.bits >> 5) & 1) != 0)
179    }
180    ///Bit 6 - Timer 12 clock enable
181    #[inline(always)]
182    pub fn tim12en(&self) -> TIM12EN_R {
183        TIM12EN_R::new(((self.bits >> 6) & 1) != 0)
184    }
185    ///Bit 7 - Timer 13 clock enable
186    #[inline(always)]
187    pub fn tim13en(&self) -> TIM13EN_R {
188        TIM13EN_R::new(((self.bits >> 7) & 1) != 0)
189    }
190    ///Bit 8 - Timer 14 clock enable
191    #[inline(always)]
192    pub fn tim14en(&self) -> TIM14EN_R {
193        TIM14EN_R::new(((self.bits >> 8) & 1) != 0)
194    }
195    ///Bit 11 - Window watchdog clock enable
196    #[inline(always)]
197    pub fn wwdgen(&self) -> WWDGEN_R {
198        WWDGEN_R::new(((self.bits >> 11) & 1) != 0)
199    }
200    ///Bit 14 - SPI 2 clock enable
201    #[inline(always)]
202    pub fn spi2en(&self) -> SPI2EN_R {
203        SPI2EN_R::new(((self.bits >> 14) & 1) != 0)
204    }
205    ///Bit 15 - SPI 3 clock enable
206    #[inline(always)]
207    pub fn spi3en(&self) -> SPI3EN_R {
208        SPI3EN_R::new(((self.bits >> 15) & 1) != 0)
209    }
210    ///Bit 17 - USART 2 clock enable
211    #[inline(always)]
212    pub fn usart2en(&self) -> USART2EN_R {
213        USART2EN_R::new(((self.bits >> 17) & 1) != 0)
214    }
215    ///Bit 18 - USART 3 clock enable
216    #[inline(always)]
217    pub fn usart3en(&self) -> USART3EN_R {
218        USART3EN_R::new(((self.bits >> 18) & 1) != 0)
219    }
220    ///Bit 19 - UART 4 clock enable
221    #[inline(always)]
222    pub fn uart4en(&self) -> UART4EN_R {
223        UART4EN_R::new(((self.bits >> 19) & 1) != 0)
224    }
225    ///Bit 20 - UART 5 clock enable
226    #[inline(always)]
227    pub fn uart5en(&self) -> UART5EN_R {
228        UART5EN_R::new(((self.bits >> 20) & 1) != 0)
229    }
230    ///Bit 21 - I2C 1 clock enable
231    #[inline(always)]
232    pub fn i2c1en(&self) -> I2C1EN_R {
233        I2C1EN_R::new(((self.bits >> 21) & 1) != 0)
234    }
235    ///Bit 22 - I2C 2 clock enable
236    #[inline(always)]
237    pub fn i2c2en(&self) -> I2C2EN_R {
238        I2C2EN_R::new(((self.bits >> 22) & 1) != 0)
239    }
240    ///Bit 23 - USB clock enable
241    #[inline(always)]
242    pub fn usben(&self) -> USBEN_R {
243        USBEN_R::new(((self.bits >> 23) & 1) != 0)
244    }
245    ///Bit 25 - CAN clock enable
246    #[inline(always)]
247    pub fn canen(&self) -> CANEN_R {
248        CANEN_R::new(((self.bits >> 25) & 1) != 0)
249    }
250    ///Bit 27 - Backup interface clock enable
251    #[inline(always)]
252    pub fn bkpen(&self) -> BKPEN_R {
253        BKPEN_R::new(((self.bits >> 27) & 1) != 0)
254    }
255    ///Bit 28 - Power interface clock enable
256    #[inline(always)]
257    pub fn pwren(&self) -> PWREN_R {
258        PWREN_R::new(((self.bits >> 28) & 1) != 0)
259    }
260    ///Bit 29 - DAC interface clock enable
261    #[inline(always)]
262    pub fn dacen(&self) -> DACEN_R {
263        DACEN_R::new(((self.bits >> 29) & 1) != 0)
264    }
265}
266impl core::fmt::Debug for R {
267    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
268        f.debug_struct("APB1ENR")
269            .field("tim2en", &self.tim2en())
270            .field("tim3en", &self.tim3en())
271            .field("tim4en", &self.tim4en())
272            .field("tim5en", &self.tim5en())
273            .field("tim6en", &self.tim6en())
274            .field("tim7en", &self.tim7en())
275            .field("tim12en", &self.tim12en())
276            .field("tim13en", &self.tim13en())
277            .field("tim14en", &self.tim14en())
278            .field("wwdgen", &self.wwdgen())
279            .field("spi2en", &self.spi2en())
280            .field("spi3en", &self.spi3en())
281            .field("usart2en", &self.usart2en())
282            .field("usart3en", &self.usart3en())
283            .field("uart4en", &self.uart4en())
284            .field("uart5en", &self.uart5en())
285            .field("i2c1en", &self.i2c1en())
286            .field("i2c2en", &self.i2c2en())
287            .field("usben", &self.usben())
288            .field("canen", &self.canen())
289            .field("bkpen", &self.bkpen())
290            .field("pwren", &self.pwren())
291            .field("dacen", &self.dacen())
292            .finish()
293    }
294}
295impl W {
296    ///Bit 0 - Timer 2 clock enable
297    #[inline(always)]
298    pub fn tim2en(&mut self) -> TIM2EN_W<APB1ENRrs> {
299        TIM2EN_W::new(self, 0)
300    }
301    ///Bit 1 - Timer 3 clock enable
302    #[inline(always)]
303    pub fn tim3en(&mut self) -> TIM3EN_W<APB1ENRrs> {
304        TIM3EN_W::new(self, 1)
305    }
306    ///Bit 2 - Timer 4 clock enable
307    #[inline(always)]
308    pub fn tim4en(&mut self) -> TIM4EN_W<APB1ENRrs> {
309        TIM4EN_W::new(self, 2)
310    }
311    ///Bit 3 - Timer 5 clock enable
312    #[inline(always)]
313    pub fn tim5en(&mut self) -> TIM5EN_W<APB1ENRrs> {
314        TIM5EN_W::new(self, 3)
315    }
316    ///Bit 4 - Timer 6 clock enable
317    #[inline(always)]
318    pub fn tim6en(&mut self) -> TIM6EN_W<APB1ENRrs> {
319        TIM6EN_W::new(self, 4)
320    }
321    ///Bit 5 - Timer 7 clock enable
322    #[inline(always)]
323    pub fn tim7en(&mut self) -> TIM7EN_W<APB1ENRrs> {
324        TIM7EN_W::new(self, 5)
325    }
326    ///Bit 6 - Timer 12 clock enable
327    #[inline(always)]
328    pub fn tim12en(&mut self) -> TIM12EN_W<APB1ENRrs> {
329        TIM12EN_W::new(self, 6)
330    }
331    ///Bit 7 - Timer 13 clock enable
332    #[inline(always)]
333    pub fn tim13en(&mut self) -> TIM13EN_W<APB1ENRrs> {
334        TIM13EN_W::new(self, 7)
335    }
336    ///Bit 8 - Timer 14 clock enable
337    #[inline(always)]
338    pub fn tim14en(&mut self) -> TIM14EN_W<APB1ENRrs> {
339        TIM14EN_W::new(self, 8)
340    }
341    ///Bit 11 - Window watchdog clock enable
342    #[inline(always)]
343    pub fn wwdgen(&mut self) -> WWDGEN_W<APB1ENRrs> {
344        WWDGEN_W::new(self, 11)
345    }
346    ///Bit 14 - SPI 2 clock enable
347    #[inline(always)]
348    pub fn spi2en(&mut self) -> SPI2EN_W<APB1ENRrs> {
349        SPI2EN_W::new(self, 14)
350    }
351    ///Bit 15 - SPI 3 clock enable
352    #[inline(always)]
353    pub fn spi3en(&mut self) -> SPI3EN_W<APB1ENRrs> {
354        SPI3EN_W::new(self, 15)
355    }
356    ///Bit 17 - USART 2 clock enable
357    #[inline(always)]
358    pub fn usart2en(&mut self) -> USART2EN_W<APB1ENRrs> {
359        USART2EN_W::new(self, 17)
360    }
361    ///Bit 18 - USART 3 clock enable
362    #[inline(always)]
363    pub fn usart3en(&mut self) -> USART3EN_W<APB1ENRrs> {
364        USART3EN_W::new(self, 18)
365    }
366    ///Bit 19 - UART 4 clock enable
367    #[inline(always)]
368    pub fn uart4en(&mut self) -> UART4EN_W<APB1ENRrs> {
369        UART4EN_W::new(self, 19)
370    }
371    ///Bit 20 - UART 5 clock enable
372    #[inline(always)]
373    pub fn uart5en(&mut self) -> UART5EN_W<APB1ENRrs> {
374        UART5EN_W::new(self, 20)
375    }
376    ///Bit 21 - I2C 1 clock enable
377    #[inline(always)]
378    pub fn i2c1en(&mut self) -> I2C1EN_W<APB1ENRrs> {
379        I2C1EN_W::new(self, 21)
380    }
381    ///Bit 22 - I2C 2 clock enable
382    #[inline(always)]
383    pub fn i2c2en(&mut self) -> I2C2EN_W<APB1ENRrs> {
384        I2C2EN_W::new(self, 22)
385    }
386    ///Bit 23 - USB clock enable
387    #[inline(always)]
388    pub fn usben(&mut self) -> USBEN_W<APB1ENRrs> {
389        USBEN_W::new(self, 23)
390    }
391    ///Bit 25 - CAN clock enable
392    #[inline(always)]
393    pub fn canen(&mut self) -> CANEN_W<APB1ENRrs> {
394        CANEN_W::new(self, 25)
395    }
396    ///Bit 27 - Backup interface clock enable
397    #[inline(always)]
398    pub fn bkpen(&mut self) -> BKPEN_W<APB1ENRrs> {
399        BKPEN_W::new(self, 27)
400    }
401    ///Bit 28 - Power interface clock enable
402    #[inline(always)]
403    pub fn pwren(&mut self) -> PWREN_W<APB1ENRrs> {
404        PWREN_W::new(self, 28)
405    }
406    ///Bit 29 - DAC interface clock enable
407    #[inline(always)]
408    pub fn dacen(&mut self) -> DACEN_W<APB1ENRrs> {
409        DACEN_W::new(self, 29)
410    }
411}
412/**APB1 peripheral clock enable register (RCC_APB1ENR)
413
414You can [`read`](crate::Reg::read) this register and get [`apb1enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
415
416See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:APB1ENR)*/
417pub struct APB1ENRrs;
418impl crate::RegisterSpec for APB1ENRrs {
419    type Ux = u32;
420}
421///`read()` method returns [`apb1enr::R`](R) reader structure
422impl crate::Readable for APB1ENRrs {}
423///`write(|w| ..)` method takes [`apb1enr::W`](W) writer structure
424impl crate::Writable for APB1ENRrs {
425    type Safety = crate::Unsafe;
426}
427///`reset()` method sets APB1ENR to value 0
428impl crate::Resettable for APB1ENRrs {}
stm32f1_staging/stm32f103/rcc/apb1enr.rs

stm32f1_staging/stm32f103/rcc/
apb1enr.rs
