stm32f1_staging/stm32f103/rcc/
ahbenr.rs

1///Register `AHBENR` reader
2pub type R = crate::R<AHBENRrs>;
3///Register `AHBENR` writer
4pub type W = crate::W<AHBENRrs>;
5/**DMA1 clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum DMA1EN {
11    ///0: The selected clock is disabled
12    Disabled = 0,
13    ///1: The selected clock is enabled
14    Enabled = 1,
15}
16impl From<DMA1EN> for bool {
17    #[inline(always)]
18    fn from(variant: DMA1EN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `DMA1EN` reader - DMA1 clock enable
23pub type DMA1EN_R = crate::BitReader<DMA1EN>;
24impl DMA1EN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> DMA1EN {
28        match self.bits {
29            false => DMA1EN::Disabled,
30            true => DMA1EN::Enabled,
31        }
32    }
33    ///The selected clock is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == DMA1EN::Disabled
37    }
38    ///The selected clock is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == DMA1EN::Enabled
42    }
43}
44///Field `DMA1EN` writer - DMA1 clock enable
45pub type DMA1EN_W<'a, REG> = crate::BitWriter<'a, REG, DMA1EN>;
46impl<'a, REG> DMA1EN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The selected clock is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(DMA1EN::Disabled)
54    }
55    ///The selected clock is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(DMA1EN::Enabled)
59    }
60}
61///Field `DMA2EN` reader - DMA2 clock enable
62pub use DMA1EN_R as DMA2EN_R;
63///Field `SRAMEN` reader - SRAM interface clock enable
64pub use DMA1EN_R as SRAMEN_R;
65///Field `FLITFEN` reader - FLITF clock enable
66pub use DMA1EN_R as FLITFEN_R;
67///Field `CRCEN` reader - CRC clock enable
68pub use DMA1EN_R as CRCEN_R;
69///Field `FSMCEN` reader - FSMC clock enable
70pub use DMA1EN_R as FSMCEN_R;
71///Field `SDIOEN` reader - SDIO clock enable
72pub use DMA1EN_R as SDIOEN_R;
73///Field `DMA2EN` writer - DMA2 clock enable
74pub use DMA1EN_W as DMA2EN_W;
75///Field `SRAMEN` writer - SRAM interface clock enable
76pub use DMA1EN_W as SRAMEN_W;
77///Field `FLITFEN` writer - FLITF clock enable
78pub use DMA1EN_W as FLITFEN_W;
79///Field `CRCEN` writer - CRC clock enable
80pub use DMA1EN_W as CRCEN_W;
81///Field `FSMCEN` writer - FSMC clock enable
82pub use DMA1EN_W as FSMCEN_W;
83///Field `SDIOEN` writer - SDIO clock enable
84pub use DMA1EN_W as SDIOEN_W;
85impl R {
86    ///Bit 0 - DMA1 clock enable
87    #[inline(always)]
88    pub fn dma1en(&self) -> DMA1EN_R {
89        DMA1EN_R::new((self.bits & 1) != 0)
90    }
91    ///Bit 1 - DMA2 clock enable
92    #[inline(always)]
93    pub fn dma2en(&self) -> DMA2EN_R {
94        DMA2EN_R::new(((self.bits >> 1) & 1) != 0)
95    }
96    ///Bit 2 - SRAM interface clock enable
97    #[inline(always)]
98    pub fn sramen(&self) -> SRAMEN_R {
99        SRAMEN_R::new(((self.bits >> 2) & 1) != 0)
100    }
101    ///Bit 4 - FLITF clock enable
102    #[inline(always)]
103    pub fn flitfen(&self) -> FLITFEN_R {
104        FLITFEN_R::new(((self.bits >> 4) & 1) != 0)
105    }
106    ///Bit 6 - CRC clock enable
107    #[inline(always)]
108    pub fn crcen(&self) -> CRCEN_R {
109        CRCEN_R::new(((self.bits >> 6) & 1) != 0)
110    }
111    ///Bit 8 - FSMC clock enable
112    #[inline(always)]
113    pub fn fsmcen(&self) -> FSMCEN_R {
114        FSMCEN_R::new(((self.bits >> 8) & 1) != 0)
115    }
116    ///Bit 10 - SDIO clock enable
117    #[inline(always)]
118    pub fn sdioen(&self) -> SDIOEN_R {
119        SDIOEN_R::new(((self.bits >> 10) & 1) != 0)
120    }
121}
122impl core::fmt::Debug for R {
123    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
124        f.debug_struct("AHBENR")
125            .field("dma1en", &self.dma1en())
126            .field("dma2en", &self.dma2en())
127            .field("sramen", &self.sramen())
128            .field("flitfen", &self.flitfen())
129            .field("crcen", &self.crcen())
130            .field("fsmcen", &self.fsmcen())
131            .field("sdioen", &self.sdioen())
132            .finish()
133    }
134}
135impl W {
136    ///Bit 0 - DMA1 clock enable
137    #[inline(always)]
138    pub fn dma1en(&mut self) -> DMA1EN_W<AHBENRrs> {
139        DMA1EN_W::new(self, 0)
140    }
141    ///Bit 1 - DMA2 clock enable
142    #[inline(always)]
143    pub fn dma2en(&mut self) -> DMA2EN_W<AHBENRrs> {
144        DMA2EN_W::new(self, 1)
145    }
146    ///Bit 2 - SRAM interface clock enable
147    #[inline(always)]
148    pub fn sramen(&mut self) -> SRAMEN_W<AHBENRrs> {
149        SRAMEN_W::new(self, 2)
150    }
151    ///Bit 4 - FLITF clock enable
152    #[inline(always)]
153    pub fn flitfen(&mut self) -> FLITFEN_W<AHBENRrs> {
154        FLITFEN_W::new(self, 4)
155    }
156    ///Bit 6 - CRC clock enable
157    #[inline(always)]
158    pub fn crcen(&mut self) -> CRCEN_W<AHBENRrs> {
159        CRCEN_W::new(self, 6)
160    }
161    ///Bit 8 - FSMC clock enable
162    #[inline(always)]
163    pub fn fsmcen(&mut self) -> FSMCEN_W<AHBENRrs> {
164        FSMCEN_W::new(self, 8)
165    }
166    ///Bit 10 - SDIO clock enable
167    #[inline(always)]
168    pub fn sdioen(&mut self) -> SDIOEN_W<AHBENRrs> {
169        SDIOEN_W::new(self, 10)
170    }
171}
172/**AHB Peripheral Clock enable register (RCC_AHBENR)
173
174You can [`read`](crate::Reg::read) this register and get [`ahbenr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbenr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
175
176See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:AHBENR)*/
177pub struct AHBENRrs;
178impl crate::RegisterSpec for AHBENRrs {
179    type Ux = u32;
180}
181///`read()` method returns [`ahbenr::R`](R) reader structure
182impl crate::Readable for AHBENRrs {}
183///`write(|w| ..)` method takes [`ahbenr::W`](W) writer structure
184impl crate::Writable for AHBENRrs {
185    type Safety = crate::Unsafe;
186}
187///`reset()` method sets AHBENR to value 0x14
188impl crate::Resettable for AHBENRrs {
189    const RESET_VALUE: u32 = 0x14;
190}
stm32f1_staging/stm32f103/rcc/ahbenr.rs

stm32f1_staging/stm32f103/rcc/
ahbenr.rs
