stm32f1_staging/stm32f103/exti/
pr.rs

1///Register `PR` reader
2pub type R = crate::R<PRrs>;
3///Register `PR` writer
4pub type W = crate::W<PRrs>;
5/**Pending bit %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum PR0R {
11    ///0: No trigger request occurred
12    NotPending = 0,
13    ///1: Selected trigger request occurred
14    Pending = 1,
15}
16impl From<PR0R> for bool {
17    #[inline(always)]
18    fn from(variant: PR0R) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `PR(0-18)` reader - Pending bit %s
23pub type PR_R = crate::BitReader<PR0R>;
24impl PR_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> PR0R {
28        match self.bits {
29            false => PR0R::NotPending,
30            true => PR0R::Pending,
31        }
32    }
33    ///No trigger request occurred
34    #[inline(always)]
35    pub fn is_not_pending(&self) -> bool {
36        *self == PR0R::NotPending
37    }
38    ///Selected trigger request occurred
39    #[inline(always)]
40    pub fn is_pending(&self) -> bool {
41        *self == PR0R::Pending
42    }
43}
44/**Pending bit %s
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum PR0W {
50    ///1: Clears pending bit
51    Clear = 1,
52}
53impl From<PR0W> for bool {
54    #[inline(always)]
55    fn from(variant: PR0W) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `PR(0-18)` writer - Pending bit %s
60pub type PR_W<'a, REG> = crate::BitWriter1C<'a, REG, PR0W>;
61impl<'a, REG> PR_W<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64{
65    ///Clears pending bit
66    #[inline(always)]
67    pub fn clear(self) -> &'a mut crate::W<REG> {
68        self.variant(PR0W::Clear)
69    }
70}
71impl R {
72    ///Pending bit (0-18)
73    ///
74    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `PR0` field.</div>
75    #[inline(always)]
76    pub fn pr(&self, n: u8) -> PR_R {
77        #[allow(clippy::no_effect)] [(); 19][n as usize];
78        PR_R::new(((self.bits >> n) & 1) != 0)
79    }
80    ///Iterator for array of:
81    ///Pending bit (0-18)
82    #[inline(always)]
83    pub fn pr_iter(&self) -> impl Iterator<Item = PR_R> + '_ {
84        (0..19).map(move |n| PR_R::new(((self.bits >> n) & 1) != 0))
85    }
86    ///Bit 0 - Pending bit 0
87    #[inline(always)]
88    pub fn pr0(&self) -> PR_R {
89        PR_R::new((self.bits & 1) != 0)
90    }
91    ///Bit 1 - Pending bit 1
92    #[inline(always)]
93    pub fn pr1(&self) -> PR_R {
94        PR_R::new(((self.bits >> 1) & 1) != 0)
95    }
96    ///Bit 2 - Pending bit 2
97    #[inline(always)]
98    pub fn pr2(&self) -> PR_R {
99        PR_R::new(((self.bits >> 2) & 1) != 0)
100    }
101    ///Bit 3 - Pending bit 3
102    #[inline(always)]
103    pub fn pr3(&self) -> PR_R {
104        PR_R::new(((self.bits >> 3) & 1) != 0)
105    }
106    ///Bit 4 - Pending bit 4
107    #[inline(always)]
108    pub fn pr4(&self) -> PR_R {
109        PR_R::new(((self.bits >> 4) & 1) != 0)
110    }
111    ///Bit 5 - Pending bit 5
112    #[inline(always)]
113    pub fn pr5(&self) -> PR_R {
114        PR_R::new(((self.bits >> 5) & 1) != 0)
115    }
116    ///Bit 6 - Pending bit 6
117    #[inline(always)]
118    pub fn pr6(&self) -> PR_R {
119        PR_R::new(((self.bits >> 6) & 1) != 0)
120    }
121    ///Bit 7 - Pending bit 7
122    #[inline(always)]
123    pub fn pr7(&self) -> PR_R {
124        PR_R::new(((self.bits >> 7) & 1) != 0)
125    }
126    ///Bit 8 - Pending bit 8
127    #[inline(always)]
128    pub fn pr8(&self) -> PR_R {
129        PR_R::new(((self.bits >> 8) & 1) != 0)
130    }
131    ///Bit 9 - Pending bit 9
132    #[inline(always)]
133    pub fn pr9(&self) -> PR_R {
134        PR_R::new(((self.bits >> 9) & 1) != 0)
135    }
136    ///Bit 10 - Pending bit 10
137    #[inline(always)]
138    pub fn pr10(&self) -> PR_R {
139        PR_R::new(((self.bits >> 10) & 1) != 0)
140    }
141    ///Bit 11 - Pending bit 11
142    #[inline(always)]
143    pub fn pr11(&self) -> PR_R {
144        PR_R::new(((self.bits >> 11) & 1) != 0)
145    }
146    ///Bit 12 - Pending bit 12
147    #[inline(always)]
148    pub fn pr12(&self) -> PR_R {
149        PR_R::new(((self.bits >> 12) & 1) != 0)
150    }
151    ///Bit 13 - Pending bit 13
152    #[inline(always)]
153    pub fn pr13(&self) -> PR_R {
154        PR_R::new(((self.bits >> 13) & 1) != 0)
155    }
156    ///Bit 14 - Pending bit 14
157    #[inline(always)]
158    pub fn pr14(&self) -> PR_R {
159        PR_R::new(((self.bits >> 14) & 1) != 0)
160    }
161    ///Bit 15 - Pending bit 15
162    #[inline(always)]
163    pub fn pr15(&self) -> PR_R {
164        PR_R::new(((self.bits >> 15) & 1) != 0)
165    }
166    ///Bit 16 - Pending bit 16
167    #[inline(always)]
168    pub fn pr16(&self) -> PR_R {
169        PR_R::new(((self.bits >> 16) & 1) != 0)
170    }
171    ///Bit 17 - Pending bit 17
172    #[inline(always)]
173    pub fn pr17(&self) -> PR_R {
174        PR_R::new(((self.bits >> 17) & 1) != 0)
175    }
176    ///Bit 18 - Pending bit 18
177    #[inline(always)]
178    pub fn pr18(&self) -> PR_R {
179        PR_R::new(((self.bits >> 18) & 1) != 0)
180    }
181}
182impl core::fmt::Debug for R {
183    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
184        f.debug_struct("PR")
185            .field("pr0", &self.pr0())
186            .field("pr1", &self.pr1())
187            .field("pr2", &self.pr2())
188            .field("pr3", &self.pr3())
189            .field("pr4", &self.pr4())
190            .field("pr5", &self.pr5())
191            .field("pr6", &self.pr6())
192            .field("pr7", &self.pr7())
193            .field("pr8", &self.pr8())
194            .field("pr9", &self.pr9())
195            .field("pr10", &self.pr10())
196            .field("pr11", &self.pr11())
197            .field("pr12", &self.pr12())
198            .field("pr13", &self.pr13())
199            .field("pr14", &self.pr14())
200            .field("pr15", &self.pr15())
201            .field("pr16", &self.pr16())
202            .field("pr17", &self.pr17())
203            .field("pr18", &self.pr18())
204            .finish()
205    }
206}
207impl W {
208    ///Pending bit (0-18)
209    ///
210    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `PR0` field.</div>
211    #[inline(always)]
212    pub fn pr(&mut self, n: u8) -> PR_W<PRrs> {
213        #[allow(clippy::no_effect)] [(); 19][n as usize];
214        PR_W::new(self, n)
215    }
216    ///Bit 0 - Pending bit 0
217    #[inline(always)]
218    pub fn pr0(&mut self) -> PR_W<PRrs> {
219        PR_W::new(self, 0)
220    }
221    ///Bit 1 - Pending bit 1
222    #[inline(always)]
223    pub fn pr1(&mut self) -> PR_W<PRrs> {
224        PR_W::new(self, 1)
225    }
226    ///Bit 2 - Pending bit 2
227    #[inline(always)]
228    pub fn pr2(&mut self) -> PR_W<PRrs> {
229        PR_W::new(self, 2)
230    }
231    ///Bit 3 - Pending bit 3
232    #[inline(always)]
233    pub fn pr3(&mut self) -> PR_W<PRrs> {
234        PR_W::new(self, 3)
235    }
236    ///Bit 4 - Pending bit 4
237    #[inline(always)]
238    pub fn pr4(&mut self) -> PR_W<PRrs> {
239        PR_W::new(self, 4)
240    }
241    ///Bit 5 - Pending bit 5
242    #[inline(always)]
243    pub fn pr5(&mut self) -> PR_W<PRrs> {
244        PR_W::new(self, 5)
245    }
246    ///Bit 6 - Pending bit 6
247    #[inline(always)]
248    pub fn pr6(&mut self) -> PR_W<PRrs> {
249        PR_W::new(self, 6)
250    }
251    ///Bit 7 - Pending bit 7
252    #[inline(always)]
253    pub fn pr7(&mut self) -> PR_W<PRrs> {
254        PR_W::new(self, 7)
255    }
256    ///Bit 8 - Pending bit 8
257    #[inline(always)]
258    pub fn pr8(&mut self) -> PR_W<PRrs> {
259        PR_W::new(self, 8)
260    }
261    ///Bit 9 - Pending bit 9
262    #[inline(always)]
263    pub fn pr9(&mut self) -> PR_W<PRrs> {
264        PR_W::new(self, 9)
265    }
266    ///Bit 10 - Pending bit 10
267    #[inline(always)]
268    pub fn pr10(&mut self) -> PR_W<PRrs> {
269        PR_W::new(self, 10)
270    }
271    ///Bit 11 - Pending bit 11
272    #[inline(always)]
273    pub fn pr11(&mut self) -> PR_W<PRrs> {
274        PR_W::new(self, 11)
275    }
276    ///Bit 12 - Pending bit 12
277    #[inline(always)]
278    pub fn pr12(&mut self) -> PR_W<PRrs> {
279        PR_W::new(self, 12)
280    }
281    ///Bit 13 - Pending bit 13
282    #[inline(always)]
283    pub fn pr13(&mut self) -> PR_W<PRrs> {
284        PR_W::new(self, 13)
285    }
286    ///Bit 14 - Pending bit 14
287    #[inline(always)]
288    pub fn pr14(&mut self) -> PR_W<PRrs> {
289        PR_W::new(self, 14)
290    }
291    ///Bit 15 - Pending bit 15
292    #[inline(always)]
293    pub fn pr15(&mut self) -> PR_W<PRrs> {
294        PR_W::new(self, 15)
295    }
296    ///Bit 16 - Pending bit 16
297    #[inline(always)]
298    pub fn pr16(&mut self) -> PR_W<PRrs> {
299        PR_W::new(self, 16)
300    }
301    ///Bit 17 - Pending bit 17
302    #[inline(always)]
303    pub fn pr17(&mut self) -> PR_W<PRrs> {
304        PR_W::new(self, 17)
305    }
306    ///Bit 18 - Pending bit 18
307    #[inline(always)]
308    pub fn pr18(&mut self) -> PR_W<PRrs> {
309        PR_W::new(self, 18)
310    }
311}
312/**Pending register (EXTI_PR)
313
314You can [`read`](crate::Reg::read) this register and get [`pr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
315
316See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#EXTI:PR)*/
317pub struct PRrs;
318impl crate::RegisterSpec for PRrs {
319    type Ux = u32;
320}
321///`read()` method returns [`pr::R`](R) reader structure
322impl crate::Readable for PRrs {}
323///`write(|w| ..)` method takes [`pr::W`](W) writer structure
324impl crate::Writable for PRrs {
325    type Safety = crate::Unsafe;
326    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0007_ffff;
327}
328///`reset()` method sets PR to value 0
329impl crate::Resettable for PRrs {}
stm32f1_staging/stm32f103/exti/pr.rs

stm32f1_staging/stm32f103/exti/
pr.rs
