stm32f1_staging/stm32f103/dac/
dhr12ld.rs

1///Register `DHR12LD` reader
2pub type R = crate::R<DHR12LDrs>;
3///Register `DHR12LD` writer
4pub type W = crate::W<DHR12LDrs>;
5///Field `DACC1DHR` reader - DAC channel1 12-bit left-aligned data
6pub type DACC1DHR_R = crate::FieldReader<u16>;
7///Field `DACC1DHR` writer - DAC channel1 12-bit left-aligned data
8pub type DACC1DHR_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16, crate::Safe>;
9///Field `DACC2DHR` reader - DAC channel2 12-bit right-aligned data
10pub type DACC2DHR_R = crate::FieldReader<u16>;
11///Field `DACC2DHR` writer - DAC channel2 12-bit right-aligned data
12pub type DACC2DHR_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16, crate::Safe>;
13impl R {
14    ///Bits 4:15 - DAC channel1 12-bit left-aligned data
15    #[inline(always)]
16    pub fn dacc1dhr(&self) -> DACC1DHR_R {
17        DACC1DHR_R::new(((self.bits >> 4) & 0x0fff) as u16)
18    }
19    ///Bits 20:31 - DAC channel2 12-bit right-aligned data
20    #[inline(always)]
21    pub fn dacc2dhr(&self) -> DACC2DHR_R {
22        DACC2DHR_R::new(((self.bits >> 20) & 0x0fff) as u16)
23    }
24}
25impl core::fmt::Debug for R {
26    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
27        f.debug_struct("DHR12LD")
28            .field("dacc1dhr", &self.dacc1dhr())
29            .field("dacc2dhr", &self.dacc2dhr())
30            .finish()
31    }
32}
33impl W {
34    ///Bits 4:15 - DAC channel1 12-bit left-aligned data
35    #[inline(always)]
36    pub fn dacc1dhr(&mut self) -> DACC1DHR_W<DHR12LDrs> {
37        DACC1DHR_W::new(self, 4)
38    }
39    ///Bits 20:31 - DAC channel2 12-bit right-aligned data
40    #[inline(always)]
41    pub fn dacc2dhr(&mut self) -> DACC2DHR_W<DHR12LDrs> {
42        DACC2DHR_W::new(self, 20)
43    }
44}
45/**DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
46
47You can [`read`](crate::Reg::read) this register and get [`dhr12ld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12ld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
48
49See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#DAC:DHR12LD)*/
50pub struct DHR12LDrs;
51impl crate::RegisterSpec for DHR12LDrs {
52    type Ux = u32;
53}
54///`read()` method returns [`dhr12ld::R`](R) reader structure
55impl crate::Readable for DHR12LDrs {}
56///`write(|w| ..)` method takes [`dhr12ld::W`](W) writer structure
57impl crate::Writable for DHR12LDrs {
58    type Safety = crate::Unsafe;
59}
60///`reset()` method sets DHR12LD to value 0
61impl crate::Resettable for DHR12LDrs {}
stm32f1_staging/stm32f103/dac/dhr12ld.rs

stm32f1_staging/stm32f103/dac/
dhr12ld.rs
