stm32f1_staging/stm32f103/dac/
dhr12l2.rs

1///Register `DHR12L2` reader
2pub type R = crate::R<DHR12L2rs>;
3///Register `DHR12L2` writer
4pub type W = crate::W<DHR12L2rs>;
5///Field `DACC2DHR` reader - DAC channel2 12-bit left-aligned data
6pub type DACC2DHR_R = crate::FieldReader<u16>;
7///Field `DACC2DHR` writer - DAC channel2 12-bit left-aligned data
8pub type DACC2DHR_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16, crate::Safe>;
9impl R {
10    ///Bits 4:15 - DAC channel2 12-bit left-aligned data
11    #[inline(always)]
12    pub fn dacc2dhr(&self) -> DACC2DHR_R {
13        DACC2DHR_R::new(((self.bits >> 4) & 0x0fff) as u16)
14    }
15}
16impl core::fmt::Debug for R {
17    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18        f.debug_struct("DHR12L2").field("dacc2dhr", &self.dacc2dhr()).finish()
19    }
20}
21impl W {
22    ///Bits 4:15 - DAC channel2 12-bit left-aligned data
23    #[inline(always)]
24    pub fn dacc2dhr(&mut self) -> DACC2DHR_W<DHR12L2rs> {
25        DACC2DHR_W::new(self, 4)
26    }
27}
28/**DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
29
30You can [`read`](crate::Reg::read) this register and get [`dhr12l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
31
32See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#DAC:DHR12L2)*/
33pub struct DHR12L2rs;
34impl crate::RegisterSpec for DHR12L2rs {
35    type Ux = u32;
36}
37///`read()` method returns [`dhr12l2::R`](R) reader structure
38impl crate::Readable for DHR12L2rs {}
39///`write(|w| ..)` method takes [`dhr12l2::W`](W) writer structure
40impl crate::Writable for DHR12L2rs {
41    type Safety = crate::Unsafe;
42}
43///`reset()` method sets DHR12L2 to value 0
44impl crate::Resettable for DHR12L2rs {}
stm32f1_staging/stm32f103/dac/dhr12l2.rs

stm32f1_staging/stm32f103/dac/
dhr12l2.rs
