stm32f1_staging/stm32f103/can/
mcr.rs

1///Register `MCR` reader
2pub type R = crate::R<MCRrs>;
3///Register `MCR` writer
4pub type W = crate::W<MCRrs>;
5///Field `INRQ` reader - INRQ
6pub type INRQ_R = crate::BitReader;
7///Field `INRQ` writer - INRQ
8pub type INRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `SLEEP` reader - SLEEP
10pub type SLEEP_R = crate::BitReader;
11///Field `SLEEP` writer - SLEEP
12pub type SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `TXFP` reader - TXFP
14pub type TXFP_R = crate::BitReader;
15///Field `TXFP` writer - TXFP
16pub type TXFP_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `RFLM` reader - RFLM
18pub type RFLM_R = crate::BitReader;
19///Field `RFLM` writer - RFLM
20pub type RFLM_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `NART` reader - NART
22pub type NART_R = crate::BitReader;
23///Field `NART` writer - NART
24pub type NART_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `AWUM` reader - AWUM
26pub type AWUM_R = crate::BitReader;
27///Field `AWUM` writer - AWUM
28pub type AWUM_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `ABOM` reader - ABOM
30pub type ABOM_R = crate::BitReader;
31///Field `ABOM` writer - ABOM
32pub type ABOM_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `TTCM` reader - TTCM
34pub type TTCM_R = crate::BitReader;
35///Field `TTCM` writer - TTCM
36pub type TTCM_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `RESET` reader - RESET
38pub type RESET_R = crate::BitReader;
39///Field `RESET` writer - RESET
40pub type RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `DBF` reader - DBF
42pub type DBF_R = crate::BitReader;
43///Field `DBF` writer - DBF
44pub type DBF_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    ///Bit 0 - INRQ
47    #[inline(always)]
48    pub fn inrq(&self) -> INRQ_R {
49        INRQ_R::new((self.bits & 1) != 0)
50    }
51    ///Bit 1 - SLEEP
52    #[inline(always)]
53    pub fn sleep(&self) -> SLEEP_R {
54        SLEEP_R::new(((self.bits >> 1) & 1) != 0)
55    }
56    ///Bit 2 - TXFP
57    #[inline(always)]
58    pub fn txfp(&self) -> TXFP_R {
59        TXFP_R::new(((self.bits >> 2) & 1) != 0)
60    }
61    ///Bit 3 - RFLM
62    #[inline(always)]
63    pub fn rflm(&self) -> RFLM_R {
64        RFLM_R::new(((self.bits >> 3) & 1) != 0)
65    }
66    ///Bit 4 - NART
67    #[inline(always)]
68    pub fn nart(&self) -> NART_R {
69        NART_R::new(((self.bits >> 4) & 1) != 0)
70    }
71    ///Bit 5 - AWUM
72    #[inline(always)]
73    pub fn awum(&self) -> AWUM_R {
74        AWUM_R::new(((self.bits >> 5) & 1) != 0)
75    }
76    ///Bit 6 - ABOM
77    #[inline(always)]
78    pub fn abom(&self) -> ABOM_R {
79        ABOM_R::new(((self.bits >> 6) & 1) != 0)
80    }
81    ///Bit 7 - TTCM
82    #[inline(always)]
83    pub fn ttcm(&self) -> TTCM_R {
84        TTCM_R::new(((self.bits >> 7) & 1) != 0)
85    }
86    ///Bit 15 - RESET
87    #[inline(always)]
88    pub fn reset(&self) -> RESET_R {
89        RESET_R::new(((self.bits >> 15) & 1) != 0)
90    }
91    ///Bit 16 - DBF
92    #[inline(always)]
93    pub fn dbf(&self) -> DBF_R {
94        DBF_R::new(((self.bits >> 16) & 1) != 0)
95    }
96}
97impl core::fmt::Debug for R {
98    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
99        f.debug_struct("MCR")
100            .field("dbf", &self.dbf())
101            .field("reset", &self.reset())
102            .field("ttcm", &self.ttcm())
103            .field("abom", &self.abom())
104            .field("awum", &self.awum())
105            .field("nart", &self.nart())
106            .field("rflm", &self.rflm())
107            .field("txfp", &self.txfp())
108            .field("sleep", &self.sleep())
109            .field("inrq", &self.inrq())
110            .finish()
111    }
112}
113impl W {
114    ///Bit 0 - INRQ
115    #[inline(always)]
116    pub fn inrq(&mut self) -> INRQ_W<MCRrs> {
117        INRQ_W::new(self, 0)
118    }
119    ///Bit 1 - SLEEP
120    #[inline(always)]
121    pub fn sleep(&mut self) -> SLEEP_W<MCRrs> {
122        SLEEP_W::new(self, 1)
123    }
124    ///Bit 2 - TXFP
125    #[inline(always)]
126    pub fn txfp(&mut self) -> TXFP_W<MCRrs> {
127        TXFP_W::new(self, 2)
128    }
129    ///Bit 3 - RFLM
130    #[inline(always)]
131    pub fn rflm(&mut self) -> RFLM_W<MCRrs> {
132        RFLM_W::new(self, 3)
133    }
134    ///Bit 4 - NART
135    #[inline(always)]
136    pub fn nart(&mut self) -> NART_W<MCRrs> {
137        NART_W::new(self, 4)
138    }
139    ///Bit 5 - AWUM
140    #[inline(always)]
141    pub fn awum(&mut self) -> AWUM_W<MCRrs> {
142        AWUM_W::new(self, 5)
143    }
144    ///Bit 6 - ABOM
145    #[inline(always)]
146    pub fn abom(&mut self) -> ABOM_W<MCRrs> {
147        ABOM_W::new(self, 6)
148    }
149    ///Bit 7 - TTCM
150    #[inline(always)]
151    pub fn ttcm(&mut self) -> TTCM_W<MCRrs> {
152        TTCM_W::new(self, 7)
153    }
154    ///Bit 15 - RESET
155    #[inline(always)]
156    pub fn reset(&mut self) -> RESET_W<MCRrs> {
157        RESET_W::new(self, 15)
158    }
159    ///Bit 16 - DBF
160    #[inline(always)]
161    pub fn dbf(&mut self) -> DBF_W<MCRrs> {
162        DBF_W::new(self, 16)
163    }
164}
165/**CAN_MCR
166
167You can [`read`](crate::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
168
169See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#CAN:MCR)*/
170pub struct MCRrs;
171impl crate::RegisterSpec for MCRrs {
172    type Ux = u32;
173}
174///`read()` method returns [`mcr::R`](R) reader structure
175impl crate::Readable for MCRrs {}
176///`write(|w| ..)` method takes [`mcr::W`](W) writer structure
177impl crate::Writable for MCRrs {
178    type Safety = crate::Unsafe;
179}
180///`reset()` method sets MCR to value 0
181impl crate::Resettable for MCRrs {}
stm32f1_staging/stm32f103/can/mcr.rs

stm32f1_staging/stm32f103/can/
mcr.rs
