stm32f1_staging/stm32f102/spi1/
sr.rs

1///Register `SR` reader
2pub type R = crate::R<SRrs>;
3///Register `SR` writer
4pub type W = crate::W<SRrs>;
5/**Receive buffer not empty
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum RXNE {
11    ///0: Rx buffer empty
12    Empty = 0,
13    ///1: Rx buffer not empty
14    NotEmpty = 1,
15}
16impl From<RXNE> for bool {
17    #[inline(always)]
18    fn from(variant: RXNE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `RXNE` reader - Receive buffer not empty
23pub type RXNE_R = crate::BitReader<RXNE>;
24impl RXNE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> RXNE {
28        match self.bits {
29            false => RXNE::Empty,
30            true => RXNE::NotEmpty,
31        }
32    }
33    ///Rx buffer empty
34    #[inline(always)]
35    pub fn is_empty(&self) -> bool {
36        *self == RXNE::Empty
37    }
38    ///Rx buffer not empty
39    #[inline(always)]
40    pub fn is_not_empty(&self) -> bool {
41        *self == RXNE::NotEmpty
42    }
43}
44/**Transmit buffer empty
45
46Value on reset: 1*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum TXE {
50    ///0: Tx buffer not empty
51    NotEmpty = 0,
52    ///1: Tx buffer empty
53    Empty = 1,
54}
55impl From<TXE> for bool {
56    #[inline(always)]
57    fn from(variant: TXE) -> Self {
58        variant as u8 != 0
59    }
60}
61///Field `TXE` reader - Transmit buffer empty
62pub type TXE_R = crate::BitReader<TXE>;
63impl TXE_R {
64    ///Get enumerated values variant
65    #[inline(always)]
66    pub const fn variant(&self) -> TXE {
67        match self.bits {
68            false => TXE::NotEmpty,
69            true => TXE::Empty,
70        }
71    }
72    ///Tx buffer not empty
73    #[inline(always)]
74    pub fn is_not_empty(&self) -> bool {
75        *self == TXE::NotEmpty
76    }
77    ///Tx buffer empty
78    #[inline(always)]
79    pub fn is_empty(&self) -> bool {
80        *self == TXE::Empty
81    }
82}
83///Field `CHSIDE` reader - Channel side
84pub type CHSIDE_R = crate::BitReader;
85///Field `UDR` reader - Underrun flag
86pub type UDR_R = crate::BitReader;
87/**CRC error flag
88
89Value on reset: 0*/
90#[cfg_attr(feature = "defmt", derive(defmt::Format))]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92pub enum CRCERRR {
93    ///0: CRC value received matches the SPIx_RXCRCR value
94    Match = 0,
95    ///1: CRC value received does not match the SPIx_RXCRCR value
96    NoMatch = 1,
97}
98impl From<CRCERRR> for bool {
99    #[inline(always)]
100    fn from(variant: CRCERRR) -> Self {
101        variant as u8 != 0
102    }
103}
104///Field `CRCERR` reader - CRC error flag
105pub type CRCERR_R = crate::BitReader<CRCERRR>;
106impl CRCERR_R {
107    ///Get enumerated values variant
108    #[inline(always)]
109    pub const fn variant(&self) -> CRCERRR {
110        match self.bits {
111            false => CRCERRR::Match,
112            true => CRCERRR::NoMatch,
113        }
114    }
115    ///CRC value received matches the SPIx_RXCRCR value
116    #[inline(always)]
117    pub fn is_match(&self) -> bool {
118        *self == CRCERRR::Match
119    }
120    ///CRC value received does not match the SPIx_RXCRCR value
121    #[inline(always)]
122    pub fn is_no_match(&self) -> bool {
123        *self == CRCERRR::NoMatch
124    }
125}
126/**CRC error flag
127
128Value on reset: 0*/
129#[cfg_attr(feature = "defmt", derive(defmt::Format))]
130#[derive(Clone, Copy, Debug, PartialEq, Eq)]
131pub enum CRCERRW {
132    ///0: Clear flag
133    Clear = 0,
134}
135impl From<CRCERRW> for bool {
136    #[inline(always)]
137    fn from(variant: CRCERRW) -> Self {
138        variant as u8 != 0
139    }
140}
141///Field `CRCERR` writer - CRC error flag
142pub type CRCERR_W<'a, REG> = crate::BitWriter0C<'a, REG, CRCERRW>;
143impl<'a, REG> CRCERR_W<'a, REG>
144where
145    REG: crate::Writable + crate::RegisterSpec,
146{
147    ///Clear flag
148    #[inline(always)]
149    pub fn clear(self) -> &'a mut crate::W<REG> {
150        self.variant(CRCERRW::Clear)
151    }
152}
153/**Mode fault
154
155Value on reset: 0*/
156#[cfg_attr(feature = "defmt", derive(defmt::Format))]
157#[derive(Clone, Copy, Debug, PartialEq, Eq)]
158pub enum MODFR {
159    ///0: No mode fault occurred
160    NoFault = 0,
161    ///1: Mode fault occurred
162    Fault = 1,
163}
164impl From<MODFR> for bool {
165    #[inline(always)]
166    fn from(variant: MODFR) -> Self {
167        variant as u8 != 0
168    }
169}
170///Field `MODF` reader - Mode fault
171pub type MODF_R = crate::BitReader<MODFR>;
172impl MODF_R {
173    ///Get enumerated values variant
174    #[inline(always)]
175    pub const fn variant(&self) -> MODFR {
176        match self.bits {
177            false => MODFR::NoFault,
178            true => MODFR::Fault,
179        }
180    }
181    ///No mode fault occurred
182    #[inline(always)]
183    pub fn is_no_fault(&self) -> bool {
184        *self == MODFR::NoFault
185    }
186    ///Mode fault occurred
187    #[inline(always)]
188    pub fn is_fault(&self) -> bool {
189        *self == MODFR::Fault
190    }
191}
192/**Overrun flag
193
194Value on reset: 0*/
195#[cfg_attr(feature = "defmt", derive(defmt::Format))]
196#[derive(Clone, Copy, Debug, PartialEq, Eq)]
197pub enum OVRR {
198    ///0: No overrun occurred
199    NoOverrun = 0,
200    ///1: Overrun occurred
201    Overrun = 1,
202}
203impl From<OVRR> for bool {
204    #[inline(always)]
205    fn from(variant: OVRR) -> Self {
206        variant as u8 != 0
207    }
208}
209///Field `OVR` reader - Overrun flag
210pub type OVR_R = crate::BitReader<OVRR>;
211impl OVR_R {
212    ///Get enumerated values variant
213    #[inline(always)]
214    pub const fn variant(&self) -> OVRR {
215        match self.bits {
216            false => OVRR::NoOverrun,
217            true => OVRR::Overrun,
218        }
219    }
220    ///No overrun occurred
221    #[inline(always)]
222    pub fn is_no_overrun(&self) -> bool {
223        *self == OVRR::NoOverrun
224    }
225    ///Overrun occurred
226    #[inline(always)]
227    pub fn is_overrun(&self) -> bool {
228        *self == OVRR::Overrun
229    }
230}
231/**Busy flag
232
233Value on reset: 0*/
234#[cfg_attr(feature = "defmt", derive(defmt::Format))]
235#[derive(Clone, Copy, Debug, PartialEq, Eq)]
236pub enum BSYR {
237    ///0: SPI not busy
238    NotBusy = 0,
239    ///1: SPI busy
240    Busy = 1,
241}
242impl From<BSYR> for bool {
243    #[inline(always)]
244    fn from(variant: BSYR) -> Self {
245        variant as u8 != 0
246    }
247}
248///Field `BSY` reader - Busy flag
249pub type BSY_R = crate::BitReader<BSYR>;
250impl BSY_R {
251    ///Get enumerated values variant
252    #[inline(always)]
253    pub const fn variant(&self) -> BSYR {
254        match self.bits {
255            false => BSYR::NotBusy,
256            true => BSYR::Busy,
257        }
258    }
259    ///SPI not busy
260    #[inline(always)]
261    pub fn is_not_busy(&self) -> bool {
262        *self == BSYR::NotBusy
263    }
264    ///SPI busy
265    #[inline(always)]
266    pub fn is_busy(&self) -> bool {
267        *self == BSYR::Busy
268    }
269}
270impl R {
271    ///Bit 0 - Receive buffer not empty
272    #[inline(always)]
273    pub fn rxne(&self) -> RXNE_R {
274        RXNE_R::new((self.bits & 1) != 0)
275    }
276    ///Bit 1 - Transmit buffer empty
277    #[inline(always)]
278    pub fn txe(&self) -> TXE_R {
279        TXE_R::new(((self.bits >> 1) & 1) != 0)
280    }
281    ///Bit 2 - Channel side
282    #[inline(always)]
283    pub fn chside(&self) -> CHSIDE_R {
284        CHSIDE_R::new(((self.bits >> 2) & 1) != 0)
285    }
286    ///Bit 3 - Underrun flag
287    #[inline(always)]
288    pub fn udr(&self) -> UDR_R {
289        UDR_R::new(((self.bits >> 3) & 1) != 0)
290    }
291    ///Bit 4 - CRC error flag
292    #[inline(always)]
293    pub fn crcerr(&self) -> CRCERR_R {
294        CRCERR_R::new(((self.bits >> 4) & 1) != 0)
295    }
296    ///Bit 5 - Mode fault
297    #[inline(always)]
298    pub fn modf(&self) -> MODF_R {
299        MODF_R::new(((self.bits >> 5) & 1) != 0)
300    }
301    ///Bit 6 - Overrun flag
302    #[inline(always)]
303    pub fn ovr(&self) -> OVR_R {
304        OVR_R::new(((self.bits >> 6) & 1) != 0)
305    }
306    ///Bit 7 - Busy flag
307    #[inline(always)]
308    pub fn bsy(&self) -> BSY_R {
309        BSY_R::new(((self.bits >> 7) & 1) != 0)
310    }
311}
312impl core::fmt::Debug for R {
313    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
314        f.debug_struct("SR")
315            .field("bsy", &self.bsy())
316            .field("ovr", &self.ovr())
317            .field("modf", &self.modf())
318            .field("crcerr", &self.crcerr())
319            .field("udr", &self.udr())
320            .field("chside", &self.chside())
321            .field("txe", &self.txe())
322            .field("rxne", &self.rxne())
323            .finish()
324    }
325}
326impl W {
327    ///Bit 4 - CRC error flag
328    #[inline(always)]
329    pub fn crcerr(&mut self) -> CRCERR_W<SRrs> {
330        CRCERR_W::new(self, 4)
331    }
332}
333/**status register
334
335You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
336
337See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SPI1:SR)*/
338pub struct SRrs;
339impl crate::RegisterSpec for SRrs {
340    type Ux = u16;
341}
342///`read()` method returns [`sr::R`](R) reader structure
343impl crate::Readable for SRrs {}
344///`write(|w| ..)` method takes [`sr::W`](W) writer structure
345impl crate::Writable for SRrs {
346    type Safety = crate::Unsafe;
347    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0x10;
348}
349///`reset()` method sets SR to value 0x02
350impl crate::Resettable for SRrs {
351    const RESET_VALUE: u16 = 0x02;
352}
stm32f1_staging/stm32f102/spi1/sr.rs

stm32f1_staging/stm32f102/spi1/
sr.rs
