stm32f1_staging/stm32f102/spi1/
i2scfgr.rs

1///Register `I2SCFGR` reader
2pub type R = crate::R<I2SCFGRrs>;
3///Register `I2SCFGR` writer
4pub type W = crate::W<I2SCFGRrs>;
5///Field `CHLEN` reader - Channel length (number of bits per audio channel)
6pub type CHLEN_R = crate::BitReader;
7///Field `CHLEN` writer - Channel length (number of bits per audio channel)
8pub type CHLEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DATLEN` reader - Data length to be transferred
10pub type DATLEN_R = crate::FieldReader;
11///Field `DATLEN` writer - Data length to be transferred
12pub type DATLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13///Field `CKPOL` reader - Steady state clock polarity
14pub type CKPOL_R = crate::BitReader;
15///Field `CKPOL` writer - Steady state clock polarity
16pub type CKPOL_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `I2SSTD` reader - I2S standard selection
18pub type I2SSTD_R = crate::FieldReader;
19///Field `I2SSTD` writer - I2S standard selection
20pub type I2SSTD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21///Field `PCMSYNC` reader - PCM frame synchronization
22pub type PCMSYNC_R = crate::BitReader;
23///Field `PCMSYNC` writer - PCM frame synchronization
24pub type PCMSYNC_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `I2SCFG` reader - I2S configuration mode
26pub type I2SCFG_R = crate::FieldReader;
27///Field `I2SCFG` writer - I2S configuration mode
28pub type I2SCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29///Field `I2SE` reader - I2S Enable
30pub type I2SE_R = crate::BitReader;
31///Field `I2SE` writer - I2S Enable
32pub type I2SE_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `I2SMOD` reader - I2S mode selection
34pub type I2SMOD_R = crate::BitReader;
35///Field `I2SMOD` writer - I2S mode selection
36pub type I2SMOD_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    ///Bit 0 - Channel length (number of bits per audio channel)
39    #[inline(always)]
40    pub fn chlen(&self) -> CHLEN_R {
41        CHLEN_R::new((self.bits & 1) != 0)
42    }
43    ///Bits 1:2 - Data length to be transferred
44    #[inline(always)]
45    pub fn datlen(&self) -> DATLEN_R {
46        DATLEN_R::new(((self.bits >> 1) & 3) as u8)
47    }
48    ///Bit 3 - Steady state clock polarity
49    #[inline(always)]
50    pub fn ckpol(&self) -> CKPOL_R {
51        CKPOL_R::new(((self.bits >> 3) & 1) != 0)
52    }
53    ///Bits 4:5 - I2S standard selection
54    #[inline(always)]
55    pub fn i2sstd(&self) -> I2SSTD_R {
56        I2SSTD_R::new(((self.bits >> 4) & 3) as u8)
57    }
58    ///Bit 7 - PCM frame synchronization
59    #[inline(always)]
60    pub fn pcmsync(&self) -> PCMSYNC_R {
61        PCMSYNC_R::new(((self.bits >> 7) & 1) != 0)
62    }
63    ///Bits 8:9 - I2S configuration mode
64    #[inline(always)]
65    pub fn i2scfg(&self) -> I2SCFG_R {
66        I2SCFG_R::new(((self.bits >> 8) & 3) as u8)
67    }
68    ///Bit 10 - I2S Enable
69    #[inline(always)]
70    pub fn i2se(&self) -> I2SE_R {
71        I2SE_R::new(((self.bits >> 10) & 1) != 0)
72    }
73    ///Bit 11 - I2S mode selection
74    #[inline(always)]
75    pub fn i2smod(&self) -> I2SMOD_R {
76        I2SMOD_R::new(((self.bits >> 11) & 1) != 0)
77    }
78}
79impl core::fmt::Debug for R {
80    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
81        f.debug_struct("I2SCFGR")
82            .field("i2smod", &self.i2smod())
83            .field("i2se", &self.i2se())
84            .field("i2scfg", &self.i2scfg())
85            .field("pcmsync", &self.pcmsync())
86            .field("i2sstd", &self.i2sstd())
87            .field("ckpol", &self.ckpol())
88            .field("datlen", &self.datlen())
89            .field("chlen", &self.chlen())
90            .finish()
91    }
92}
93impl W {
94    ///Bit 0 - Channel length (number of bits per audio channel)
95    #[inline(always)]
96    pub fn chlen(&mut self) -> CHLEN_W<I2SCFGRrs> {
97        CHLEN_W::new(self, 0)
98    }
99    ///Bits 1:2 - Data length to be transferred
100    #[inline(always)]
101    pub fn datlen(&mut self) -> DATLEN_W<I2SCFGRrs> {
102        DATLEN_W::new(self, 1)
103    }
104    ///Bit 3 - Steady state clock polarity
105    #[inline(always)]
106    pub fn ckpol(&mut self) -> CKPOL_W<I2SCFGRrs> {
107        CKPOL_W::new(self, 3)
108    }
109    ///Bits 4:5 - I2S standard selection
110    #[inline(always)]
111    pub fn i2sstd(&mut self) -> I2SSTD_W<I2SCFGRrs> {
112        I2SSTD_W::new(self, 4)
113    }
114    ///Bit 7 - PCM frame synchronization
115    #[inline(always)]
116    pub fn pcmsync(&mut self) -> PCMSYNC_W<I2SCFGRrs> {
117        PCMSYNC_W::new(self, 7)
118    }
119    ///Bits 8:9 - I2S configuration mode
120    #[inline(always)]
121    pub fn i2scfg(&mut self) -> I2SCFG_W<I2SCFGRrs> {
122        I2SCFG_W::new(self, 8)
123    }
124    ///Bit 10 - I2S Enable
125    #[inline(always)]
126    pub fn i2se(&mut self) -> I2SE_W<I2SCFGRrs> {
127        I2SE_W::new(self, 10)
128    }
129    ///Bit 11 - I2S mode selection
130    #[inline(always)]
131    pub fn i2smod(&mut self) -> I2SMOD_W<I2SCFGRrs> {
132        I2SMOD_W::new(self, 11)
133    }
134}
135/**I2S configuration register
136
137You can [`read`](crate::Reg::read) this register and get [`i2scfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2scfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
138
139See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SPI1:I2SCFGR)*/
140pub struct I2SCFGRrs;
141impl crate::RegisterSpec for I2SCFGRrs {
142    type Ux = u16;
143}
144///`read()` method returns [`i2scfgr::R`](R) reader structure
145impl crate::Readable for I2SCFGRrs {}
146///`write(|w| ..)` method takes [`i2scfgr::W`](W) writer structure
147impl crate::Writable for I2SCFGRrs {
148    type Safety = crate::Unsafe;
149}
150///`reset()` method sets I2SCFGR to value 0
151impl crate::Resettable for I2SCFGRrs {}
stm32f1_staging/stm32f102/spi1/i2scfgr.rs

stm32f1_staging/stm32f102/spi1/
i2scfgr.rs
