stm32f1_staging/stm32f102/rcc/
apb2enr.rs

1///Register `APB2ENR` reader
2pub type R = crate::R<APB2ENRrs>;
3///Register `APB2ENR` writer
4pub type W = crate::W<APB2ENRrs>;
5/**Alternate function I/O clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum AFIOEN {
11    ///0: The selected clock is disabled
12    Disabled = 0,
13    ///1: The selected clock is enabled
14    Enabled = 1,
15}
16impl From<AFIOEN> for bool {
17    #[inline(always)]
18    fn from(variant: AFIOEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `AFIOEN` reader - Alternate function I/O clock enable
23pub type AFIOEN_R = crate::BitReader<AFIOEN>;
24impl AFIOEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> AFIOEN {
28        match self.bits {
29            false => AFIOEN::Disabled,
30            true => AFIOEN::Enabled,
31        }
32    }
33    ///The selected clock is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == AFIOEN::Disabled
37    }
38    ///The selected clock is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == AFIOEN::Enabled
42    }
43}
44///Field `AFIOEN` writer - Alternate function I/O clock enable
45pub type AFIOEN_W<'a, REG> = crate::BitWriter<'a, REG, AFIOEN>;
46impl<'a, REG> AFIOEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The selected clock is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(AFIOEN::Disabled)
54    }
55    ///The selected clock is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(AFIOEN::Enabled)
59    }
60}
61///Field `IOPAEN` reader - I/O port A clock enable
62pub use AFIOEN_R as IOPAEN_R;
63///Field `IOPBEN` reader - I/O port B clock enable
64pub use AFIOEN_R as IOPBEN_R;
65///Field `IOPCEN` reader - I/O port C clock enable
66pub use AFIOEN_R as IOPCEN_R;
67///Field `IOPDEN` reader - I/O port D clock enable
68pub use AFIOEN_R as IOPDEN_R;
69///Field `ADC1EN` reader - ADC 1 interface clock enable
70pub use AFIOEN_R as ADC1EN_R;
71///Field `SPI1EN` reader - SPI 1 clock enable
72pub use AFIOEN_R as SPI1EN_R;
73///Field `USART1EN` reader - USART1 clock enable
74pub use AFIOEN_R as USART1EN_R;
75///Field `IOPAEN` writer - I/O port A clock enable
76pub use AFIOEN_W as IOPAEN_W;
77///Field `IOPBEN` writer - I/O port B clock enable
78pub use AFIOEN_W as IOPBEN_W;
79///Field `IOPCEN` writer - I/O port C clock enable
80pub use AFIOEN_W as IOPCEN_W;
81///Field `IOPDEN` writer - I/O port D clock enable
82pub use AFIOEN_W as IOPDEN_W;
83///Field `ADC1EN` writer - ADC 1 interface clock enable
84pub use AFIOEN_W as ADC1EN_W;
85///Field `SPI1EN` writer - SPI 1 clock enable
86pub use AFIOEN_W as SPI1EN_W;
87///Field `USART1EN` writer - USART1 clock enable
88pub use AFIOEN_W as USART1EN_W;
89impl R {
90    ///Bit 0 - Alternate function I/O clock enable
91    #[inline(always)]
92    pub fn afioen(&self) -> AFIOEN_R {
93        AFIOEN_R::new((self.bits & 1) != 0)
94    }
95    ///Bit 2 - I/O port A clock enable
96    #[inline(always)]
97    pub fn iopaen(&self) -> IOPAEN_R {
98        IOPAEN_R::new(((self.bits >> 2) & 1) != 0)
99    }
100    ///Bit 3 - I/O port B clock enable
101    #[inline(always)]
102    pub fn iopben(&self) -> IOPBEN_R {
103        IOPBEN_R::new(((self.bits >> 3) & 1) != 0)
104    }
105    ///Bit 4 - I/O port C clock enable
106    #[inline(always)]
107    pub fn iopcen(&self) -> IOPCEN_R {
108        IOPCEN_R::new(((self.bits >> 4) & 1) != 0)
109    }
110    ///Bit 5 - I/O port D clock enable
111    #[inline(always)]
112    pub fn iopden(&self) -> IOPDEN_R {
113        IOPDEN_R::new(((self.bits >> 5) & 1) != 0)
114    }
115    ///Bit 9 - ADC 1 interface clock enable
116    #[inline(always)]
117    pub fn adc1en(&self) -> ADC1EN_R {
118        ADC1EN_R::new(((self.bits >> 9) & 1) != 0)
119    }
120    ///Bit 12 - SPI 1 clock enable
121    #[inline(always)]
122    pub fn spi1en(&self) -> SPI1EN_R {
123        SPI1EN_R::new(((self.bits >> 12) & 1) != 0)
124    }
125    ///Bit 14 - USART1 clock enable
126    #[inline(always)]
127    pub fn usart1en(&self) -> USART1EN_R {
128        USART1EN_R::new(((self.bits >> 14) & 1) != 0)
129    }
130}
131impl core::fmt::Debug for R {
132    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
133        f.debug_struct("APB2ENR")
134            .field("afioen", &self.afioen())
135            .field("iopaen", &self.iopaen())
136            .field("iopben", &self.iopben())
137            .field("iopcen", &self.iopcen())
138            .field("iopden", &self.iopden())
139            .field("adc1en", &self.adc1en())
140            .field("spi1en", &self.spi1en())
141            .field("usart1en", &self.usart1en())
142            .finish()
143    }
144}
145impl W {
146    ///Bit 0 - Alternate function I/O clock enable
147    #[inline(always)]
148    pub fn afioen(&mut self) -> AFIOEN_W<APB2ENRrs> {
149        AFIOEN_W::new(self, 0)
150    }
151    ///Bit 2 - I/O port A clock enable
152    #[inline(always)]
153    pub fn iopaen(&mut self) -> IOPAEN_W<APB2ENRrs> {
154        IOPAEN_W::new(self, 2)
155    }
156    ///Bit 3 - I/O port B clock enable
157    #[inline(always)]
158    pub fn iopben(&mut self) -> IOPBEN_W<APB2ENRrs> {
159        IOPBEN_W::new(self, 3)
160    }
161    ///Bit 4 - I/O port C clock enable
162    #[inline(always)]
163    pub fn iopcen(&mut self) -> IOPCEN_W<APB2ENRrs> {
164        IOPCEN_W::new(self, 4)
165    }
166    ///Bit 5 - I/O port D clock enable
167    #[inline(always)]
168    pub fn iopden(&mut self) -> IOPDEN_W<APB2ENRrs> {
169        IOPDEN_W::new(self, 5)
170    }
171    ///Bit 9 - ADC 1 interface clock enable
172    #[inline(always)]
173    pub fn adc1en(&mut self) -> ADC1EN_W<APB2ENRrs> {
174        ADC1EN_W::new(self, 9)
175    }
176    ///Bit 12 - SPI 1 clock enable
177    #[inline(always)]
178    pub fn spi1en(&mut self) -> SPI1EN_W<APB2ENRrs> {
179        SPI1EN_W::new(self, 12)
180    }
181    ///Bit 14 - USART1 clock enable
182    #[inline(always)]
183    pub fn usart1en(&mut self) -> USART1EN_W<APB2ENRrs> {
184        USART1EN_W::new(self, 14)
185    }
186}
187/**APB2 peripheral clock enable register (RCC_APB2ENR)
188
189You can [`read`](crate::Reg::read) this register and get [`apb2enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
190
191See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#RCC:APB2ENR)*/
192pub struct APB2ENRrs;
193impl crate::RegisterSpec for APB2ENRrs {
194    type Ux = u32;
195}
196///`read()` method returns [`apb2enr::R`](R) reader structure
197impl crate::Readable for APB2ENRrs {}
198///`write(|w| ..)` method takes [`apb2enr::W`](W) writer structure
199impl crate::Writable for APB2ENRrs {
200    type Safety = crate::Unsafe;
201}
202///`reset()` method sets APB2ENR to value 0
203impl crate::Resettable for APB2ENRrs {}
stm32f1_staging/stm32f102/rcc/apb2enr.rs

stm32f1_staging/stm32f102/rcc/
apb2enr.rs
