stm32f1_staging/stm32f102/i2c1/
cr2.rs

1///Register `CR2` reader
2pub type R = crate::R<CR2rs>;
3///Register `CR2` writer
4pub type W = crate::W<CR2rs>;
5///Field `FREQ` reader - Peripheral clock frequency
6pub type FREQ_R = crate::FieldReader;
7///Field `FREQ` writer - Peripheral clock frequency
8pub type FREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9/**Error interrupt enable
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum ITERREN {
15    ///0: Error interrupt disabled
16    Disabled = 0,
17    ///1: Error interrupt enabled
18    Enabled = 1,
19}
20impl From<ITERREN> for bool {
21    #[inline(always)]
22    fn from(variant: ITERREN) -> Self {
23        variant as u8 != 0
24    }
25}
26///Field `ITERREN` reader - Error interrupt enable
27pub type ITERREN_R = crate::BitReader<ITERREN>;
28impl ITERREN_R {
29    ///Get enumerated values variant
30    #[inline(always)]
31    pub const fn variant(&self) -> ITERREN {
32        match self.bits {
33            false => ITERREN::Disabled,
34            true => ITERREN::Enabled,
35        }
36    }
37    ///Error interrupt disabled
38    #[inline(always)]
39    pub fn is_disabled(&self) -> bool {
40        *self == ITERREN::Disabled
41    }
42    ///Error interrupt enabled
43    #[inline(always)]
44    pub fn is_enabled(&self) -> bool {
45        *self == ITERREN::Enabled
46    }
47}
48///Field `ITERREN` writer - Error interrupt enable
49pub type ITERREN_W<'a, REG> = crate::BitWriter<'a, REG, ITERREN>;
50impl<'a, REG> ITERREN_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    ///Error interrupt disabled
55    #[inline(always)]
56    pub fn disabled(self) -> &'a mut crate::W<REG> {
57        self.variant(ITERREN::Disabled)
58    }
59    ///Error interrupt enabled
60    #[inline(always)]
61    pub fn enabled(self) -> &'a mut crate::W<REG> {
62        self.variant(ITERREN::Enabled)
63    }
64}
65/**Event interrupt enable
66
67Value on reset: 0*/
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum ITEVTEN {
71    ///0: Event interrupt disabled
72    Disabled = 0,
73    ///1: Event interrupt enabled
74    Enabled = 1,
75}
76impl From<ITEVTEN> for bool {
77    #[inline(always)]
78    fn from(variant: ITEVTEN) -> Self {
79        variant as u8 != 0
80    }
81}
82///Field `ITEVTEN` reader - Event interrupt enable
83pub type ITEVTEN_R = crate::BitReader<ITEVTEN>;
84impl ITEVTEN_R {
85    ///Get enumerated values variant
86    #[inline(always)]
87    pub const fn variant(&self) -> ITEVTEN {
88        match self.bits {
89            false => ITEVTEN::Disabled,
90            true => ITEVTEN::Enabled,
91        }
92    }
93    ///Event interrupt disabled
94    #[inline(always)]
95    pub fn is_disabled(&self) -> bool {
96        *self == ITEVTEN::Disabled
97    }
98    ///Event interrupt enabled
99    #[inline(always)]
100    pub fn is_enabled(&self) -> bool {
101        *self == ITEVTEN::Enabled
102    }
103}
104///Field `ITEVTEN` writer - Event interrupt enable
105pub type ITEVTEN_W<'a, REG> = crate::BitWriter<'a, REG, ITEVTEN>;
106impl<'a, REG> ITEVTEN_W<'a, REG>
107where
108    REG: crate::Writable + crate::RegisterSpec,
109{
110    ///Event interrupt disabled
111    #[inline(always)]
112    pub fn disabled(self) -> &'a mut crate::W<REG> {
113        self.variant(ITEVTEN::Disabled)
114    }
115    ///Event interrupt enabled
116    #[inline(always)]
117    pub fn enabled(self) -> &'a mut crate::W<REG> {
118        self.variant(ITEVTEN::Enabled)
119    }
120}
121/**Buffer interrupt enable
122
123Value on reset: 0*/
124#[cfg_attr(feature = "defmt", derive(defmt::Format))]
125#[derive(Clone, Copy, Debug, PartialEq, Eq)]
126pub enum ITBUFEN {
127    ///0: TxE=1 or RxNE=1 does not generate any interrupt
128    Disabled = 0,
129    ///1: TxE=1 or RxNE=1 generates Event interrupt
130    Enabled = 1,
131}
132impl From<ITBUFEN> for bool {
133    #[inline(always)]
134    fn from(variant: ITBUFEN) -> Self {
135        variant as u8 != 0
136    }
137}
138///Field `ITBUFEN` reader - Buffer interrupt enable
139pub type ITBUFEN_R = crate::BitReader<ITBUFEN>;
140impl ITBUFEN_R {
141    ///Get enumerated values variant
142    #[inline(always)]
143    pub const fn variant(&self) -> ITBUFEN {
144        match self.bits {
145            false => ITBUFEN::Disabled,
146            true => ITBUFEN::Enabled,
147        }
148    }
149    ///TxE=1 or RxNE=1 does not generate any interrupt
150    #[inline(always)]
151    pub fn is_disabled(&self) -> bool {
152        *self == ITBUFEN::Disabled
153    }
154    ///TxE=1 or RxNE=1 generates Event interrupt
155    #[inline(always)]
156    pub fn is_enabled(&self) -> bool {
157        *self == ITBUFEN::Enabled
158    }
159}
160///Field `ITBUFEN` writer - Buffer interrupt enable
161pub type ITBUFEN_W<'a, REG> = crate::BitWriter<'a, REG, ITBUFEN>;
162impl<'a, REG> ITBUFEN_W<'a, REG>
163where
164    REG: crate::Writable + crate::RegisterSpec,
165{
166    ///TxE=1 or RxNE=1 does not generate any interrupt
167    #[inline(always)]
168    pub fn disabled(self) -> &'a mut crate::W<REG> {
169        self.variant(ITBUFEN::Disabled)
170    }
171    ///TxE=1 or RxNE=1 generates Event interrupt
172    #[inline(always)]
173    pub fn enabled(self) -> &'a mut crate::W<REG> {
174        self.variant(ITBUFEN::Enabled)
175    }
176}
177/**DMA requests enable
178
179Value on reset: 0*/
180#[cfg_attr(feature = "defmt", derive(defmt::Format))]
181#[derive(Clone, Copy, Debug, PartialEq, Eq)]
182pub enum DMAEN {
183    ///0: DMA requests disabled
184    Disabled = 0,
185    ///1: DMA request enabled when TxE=1 or RxNE=1
186    Enabled = 1,
187}
188impl From<DMAEN> for bool {
189    #[inline(always)]
190    fn from(variant: DMAEN) -> Self {
191        variant as u8 != 0
192    }
193}
194///Field `DMAEN` reader - DMA requests enable
195pub type DMAEN_R = crate::BitReader<DMAEN>;
196impl DMAEN_R {
197    ///Get enumerated values variant
198    #[inline(always)]
199    pub const fn variant(&self) -> DMAEN {
200        match self.bits {
201            false => DMAEN::Disabled,
202            true => DMAEN::Enabled,
203        }
204    }
205    ///DMA requests disabled
206    #[inline(always)]
207    pub fn is_disabled(&self) -> bool {
208        *self == DMAEN::Disabled
209    }
210    ///DMA request enabled when TxE=1 or RxNE=1
211    #[inline(always)]
212    pub fn is_enabled(&self) -> bool {
213        *self == DMAEN::Enabled
214    }
215}
216///Field `DMAEN` writer - DMA requests enable
217pub type DMAEN_W<'a, REG> = crate::BitWriter<'a, REG, DMAEN>;
218impl<'a, REG> DMAEN_W<'a, REG>
219where
220    REG: crate::Writable + crate::RegisterSpec,
221{
222    ///DMA requests disabled
223    #[inline(always)]
224    pub fn disabled(self) -> &'a mut crate::W<REG> {
225        self.variant(DMAEN::Disabled)
226    }
227    ///DMA request enabled when TxE=1 or RxNE=1
228    #[inline(always)]
229    pub fn enabled(self) -> &'a mut crate::W<REG> {
230        self.variant(DMAEN::Enabled)
231    }
232}
233/**DMA last transfer
234
235Value on reset: 0*/
236#[cfg_attr(feature = "defmt", derive(defmt::Format))]
237#[derive(Clone, Copy, Debug, PartialEq, Eq)]
238pub enum LAST {
239    ///0: Next DMA EOT is not the last transfer
240    NotLast = 0,
241    ///1: Next DMA EOT is the last transfer
242    Last = 1,
243}
244impl From<LAST> for bool {
245    #[inline(always)]
246    fn from(variant: LAST) -> Self {
247        variant as u8 != 0
248    }
249}
250///Field `LAST` reader - DMA last transfer
251pub type LAST_R = crate::BitReader<LAST>;
252impl LAST_R {
253    ///Get enumerated values variant
254    #[inline(always)]
255    pub const fn variant(&self) -> LAST {
256        match self.bits {
257            false => LAST::NotLast,
258            true => LAST::Last,
259        }
260    }
261    ///Next DMA EOT is not the last transfer
262    #[inline(always)]
263    pub fn is_not_last(&self) -> bool {
264        *self == LAST::NotLast
265    }
266    ///Next DMA EOT is the last transfer
267    #[inline(always)]
268    pub fn is_last(&self) -> bool {
269        *self == LAST::Last
270    }
271}
272///Field `LAST` writer - DMA last transfer
273pub type LAST_W<'a, REG> = crate::BitWriter<'a, REG, LAST>;
274impl<'a, REG> LAST_W<'a, REG>
275where
276    REG: crate::Writable + crate::RegisterSpec,
277{
278    ///Next DMA EOT is not the last transfer
279    #[inline(always)]
280    pub fn not_last(self) -> &'a mut crate::W<REG> {
281        self.variant(LAST::NotLast)
282    }
283    ///Next DMA EOT is the last transfer
284    #[inline(always)]
285    pub fn last(self) -> &'a mut crate::W<REG> {
286        self.variant(LAST::Last)
287    }
288}
289impl R {
290    ///Bits 0:5 - Peripheral clock frequency
291    #[inline(always)]
292    pub fn freq(&self) -> FREQ_R {
293        FREQ_R::new((self.bits & 0x3f) as u8)
294    }
295    ///Bit 8 - Error interrupt enable
296    #[inline(always)]
297    pub fn iterren(&self) -> ITERREN_R {
298        ITERREN_R::new(((self.bits >> 8) & 1) != 0)
299    }
300    ///Bit 9 - Event interrupt enable
301    #[inline(always)]
302    pub fn itevten(&self) -> ITEVTEN_R {
303        ITEVTEN_R::new(((self.bits >> 9) & 1) != 0)
304    }
305    ///Bit 10 - Buffer interrupt enable
306    #[inline(always)]
307    pub fn itbufen(&self) -> ITBUFEN_R {
308        ITBUFEN_R::new(((self.bits >> 10) & 1) != 0)
309    }
310    ///Bit 11 - DMA requests enable
311    #[inline(always)]
312    pub fn dmaen(&self) -> DMAEN_R {
313        DMAEN_R::new(((self.bits >> 11) & 1) != 0)
314    }
315    ///Bit 12 - DMA last transfer
316    #[inline(always)]
317    pub fn last(&self) -> LAST_R {
318        LAST_R::new(((self.bits >> 12) & 1) != 0)
319    }
320}
321impl core::fmt::Debug for R {
322    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
323        f.debug_struct("CR2")
324            .field("last", &self.last())
325            .field("dmaen", &self.dmaen())
326            .field("itbufen", &self.itbufen())
327            .field("itevten", &self.itevten())
328            .field("iterren", &self.iterren())
329            .field("freq", &self.freq())
330            .finish()
331    }
332}
333impl W {
334    ///Bits 0:5 - Peripheral clock frequency
335    #[inline(always)]
336    pub fn freq(&mut self) -> FREQ_W<CR2rs> {
337        FREQ_W::new(self, 0)
338    }
339    ///Bit 8 - Error interrupt enable
340    #[inline(always)]
341    pub fn iterren(&mut self) -> ITERREN_W<CR2rs> {
342        ITERREN_W::new(self, 8)
343    }
344    ///Bit 9 - Event interrupt enable
345    #[inline(always)]
346    pub fn itevten(&mut self) -> ITEVTEN_W<CR2rs> {
347        ITEVTEN_W::new(self, 9)
348    }
349    ///Bit 10 - Buffer interrupt enable
350    #[inline(always)]
351    pub fn itbufen(&mut self) -> ITBUFEN_W<CR2rs> {
352        ITBUFEN_W::new(self, 10)
353    }
354    ///Bit 11 - DMA requests enable
355    #[inline(always)]
356    pub fn dmaen(&mut self) -> DMAEN_W<CR2rs> {
357        DMAEN_W::new(self, 11)
358    }
359    ///Bit 12 - DMA last transfer
360    #[inline(always)]
361    pub fn last(&mut self) -> LAST_W<CR2rs> {
362        LAST_W::new(self, 12)
363    }
364}
365/**Control register 2
366
367You can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
368
369See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#I2C1:CR2)*/
370pub struct CR2rs;
371impl crate::RegisterSpec for CR2rs {
372    type Ux = u16;
373}
374///`read()` method returns [`cr2::R`](R) reader structure
375impl crate::Readable for CR2rs {}
376///`write(|w| ..)` method takes [`cr2::W`](W) writer structure
377impl crate::Writable for CR2rs {
378    type Safety = crate::Unsafe;
379}
380///`reset()` method sets CR2 to value 0
381impl crate::Resettable for CR2rs {}
stm32f1_staging/stm32f102/i2c1/cr2.rs

stm32f1_staging/stm32f102/i2c1/
cr2.rs
