stm32f1_staging/stm32f102/gpioa/
odr.rs

1///Register `ODR` reader
2pub type R = crate::R<ODRrs>;
3///Register `ODR` writer
4pub type W = crate::W<ODRrs>;
5/**Port output data
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum OUTPUT_DATA {
11    ///0: Set output to logic low
12    Low = 0,
13    ///1: Set output to logic high
14    High = 1,
15}
16impl From<OUTPUT_DATA> for bool {
17    #[inline(always)]
18    fn from(variant: OUTPUT_DATA) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `ODR(0-15)` reader - Port output data
23pub type ODR_R = crate::BitReader<OUTPUT_DATA>;
24impl ODR_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> OUTPUT_DATA {
28        match self.bits {
29            false => OUTPUT_DATA::Low,
30            true => OUTPUT_DATA::High,
31        }
32    }
33    ///Set output to logic low
34    #[inline(always)]
35    pub fn is_low(&self) -> bool {
36        *self == OUTPUT_DATA::Low
37    }
38    ///Set output to logic high
39    #[inline(always)]
40    pub fn is_high(&self) -> bool {
41        *self == OUTPUT_DATA::High
42    }
43}
44///Field `ODR(0-15)` writer - Port output data
45pub type ODR_W<'a, REG> = crate::BitWriter<'a, REG, OUTPUT_DATA>;
46impl<'a, REG> ODR_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Set output to logic low
51    #[inline(always)]
52    pub fn low(self) -> &'a mut crate::W<REG> {
53        self.variant(OUTPUT_DATA::Low)
54    }
55    ///Set output to logic high
56    #[inline(always)]
57    pub fn high(self) -> &'a mut crate::W<REG> {
58        self.variant(OUTPUT_DATA::High)
59    }
60}
61impl R {
62    ///Port output data
63    ///
64    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ODR0` field.</div>
65    #[inline(always)]
66    pub fn odr(&self, n: u8) -> ODR_R {
67        #[allow(clippy::no_effect)] [(); 16][n as usize];
68        ODR_R::new(((self.bits >> n) & 1) != 0)
69    }
70    ///Iterator for array of:
71    ///Port output data
72    #[inline(always)]
73    pub fn odr_iter(&self) -> impl Iterator<Item = ODR_R> + '_ {
74        (0..16).map(move |n| ODR_R::new(((self.bits >> n) & 1) != 0))
75    }
76    ///Bit 0 - Port output data
77    #[inline(always)]
78    pub fn odr0(&self) -> ODR_R {
79        ODR_R::new((self.bits & 1) != 0)
80    }
81    ///Bit 1 - Port output data
82    #[inline(always)]
83    pub fn odr1(&self) -> ODR_R {
84        ODR_R::new(((self.bits >> 1) & 1) != 0)
85    }
86    ///Bit 2 - Port output data
87    #[inline(always)]
88    pub fn odr2(&self) -> ODR_R {
89        ODR_R::new(((self.bits >> 2) & 1) != 0)
90    }
91    ///Bit 3 - Port output data
92    #[inline(always)]
93    pub fn odr3(&self) -> ODR_R {
94        ODR_R::new(((self.bits >> 3) & 1) != 0)
95    }
96    ///Bit 4 - Port output data
97    #[inline(always)]
98    pub fn odr4(&self) -> ODR_R {
99        ODR_R::new(((self.bits >> 4) & 1) != 0)
100    }
101    ///Bit 5 - Port output data
102    #[inline(always)]
103    pub fn odr5(&self) -> ODR_R {
104        ODR_R::new(((self.bits >> 5) & 1) != 0)
105    }
106    ///Bit 6 - Port output data
107    #[inline(always)]
108    pub fn odr6(&self) -> ODR_R {
109        ODR_R::new(((self.bits >> 6) & 1) != 0)
110    }
111    ///Bit 7 - Port output data
112    #[inline(always)]
113    pub fn odr7(&self) -> ODR_R {
114        ODR_R::new(((self.bits >> 7) & 1) != 0)
115    }
116    ///Bit 8 - Port output data
117    #[inline(always)]
118    pub fn odr8(&self) -> ODR_R {
119        ODR_R::new(((self.bits >> 8) & 1) != 0)
120    }
121    ///Bit 9 - Port output data
122    #[inline(always)]
123    pub fn odr9(&self) -> ODR_R {
124        ODR_R::new(((self.bits >> 9) & 1) != 0)
125    }
126    ///Bit 10 - Port output data
127    #[inline(always)]
128    pub fn odr10(&self) -> ODR_R {
129        ODR_R::new(((self.bits >> 10) & 1) != 0)
130    }
131    ///Bit 11 - Port output data
132    #[inline(always)]
133    pub fn odr11(&self) -> ODR_R {
134        ODR_R::new(((self.bits >> 11) & 1) != 0)
135    }
136    ///Bit 12 - Port output data
137    #[inline(always)]
138    pub fn odr12(&self) -> ODR_R {
139        ODR_R::new(((self.bits >> 12) & 1) != 0)
140    }
141    ///Bit 13 - Port output data
142    #[inline(always)]
143    pub fn odr13(&self) -> ODR_R {
144        ODR_R::new(((self.bits >> 13) & 1) != 0)
145    }
146    ///Bit 14 - Port output data
147    #[inline(always)]
148    pub fn odr14(&self) -> ODR_R {
149        ODR_R::new(((self.bits >> 14) & 1) != 0)
150    }
151    ///Bit 15 - Port output data
152    #[inline(always)]
153    pub fn odr15(&self) -> ODR_R {
154        ODR_R::new(((self.bits >> 15) & 1) != 0)
155    }
156}
157impl core::fmt::Debug for R {
158    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
159        f.debug_struct("ODR")
160            .field("odr0", &self.odr0())
161            .field("odr1", &self.odr1())
162            .field("odr2", &self.odr2())
163            .field("odr3", &self.odr3())
164            .field("odr4", &self.odr4())
165            .field("odr5", &self.odr5())
166            .field("odr6", &self.odr6())
167            .field("odr7", &self.odr7())
168            .field("odr8", &self.odr8())
169            .field("odr9", &self.odr9())
170            .field("odr10", &self.odr10())
171            .field("odr11", &self.odr11())
172            .field("odr12", &self.odr12())
173            .field("odr13", &self.odr13())
174            .field("odr14", &self.odr14())
175            .field("odr15", &self.odr15())
176            .finish()
177    }
178}
179impl W {
180    ///Port output data
181    ///
182    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ODR0` field.</div>
183    #[inline(always)]
184    pub fn odr(&mut self, n: u8) -> ODR_W<ODRrs> {
185        #[allow(clippy::no_effect)] [(); 16][n as usize];
186        ODR_W::new(self, n)
187    }
188    ///Bit 0 - Port output data
189    #[inline(always)]
190    pub fn odr0(&mut self) -> ODR_W<ODRrs> {
191        ODR_W::new(self, 0)
192    }
193    ///Bit 1 - Port output data
194    #[inline(always)]
195    pub fn odr1(&mut self) -> ODR_W<ODRrs> {
196        ODR_W::new(self, 1)
197    }
198    ///Bit 2 - Port output data
199    #[inline(always)]
200    pub fn odr2(&mut self) -> ODR_W<ODRrs> {
201        ODR_W::new(self, 2)
202    }
203    ///Bit 3 - Port output data
204    #[inline(always)]
205    pub fn odr3(&mut self) -> ODR_W<ODRrs> {
206        ODR_W::new(self, 3)
207    }
208    ///Bit 4 - Port output data
209    #[inline(always)]
210    pub fn odr4(&mut self) -> ODR_W<ODRrs> {
211        ODR_W::new(self, 4)
212    }
213    ///Bit 5 - Port output data
214    #[inline(always)]
215    pub fn odr5(&mut self) -> ODR_W<ODRrs> {
216        ODR_W::new(self, 5)
217    }
218    ///Bit 6 - Port output data
219    #[inline(always)]
220    pub fn odr6(&mut self) -> ODR_W<ODRrs> {
221        ODR_W::new(self, 6)
222    }
223    ///Bit 7 - Port output data
224    #[inline(always)]
225    pub fn odr7(&mut self) -> ODR_W<ODRrs> {
226        ODR_W::new(self, 7)
227    }
228    ///Bit 8 - Port output data
229    #[inline(always)]
230    pub fn odr8(&mut self) -> ODR_W<ODRrs> {
231        ODR_W::new(self, 8)
232    }
233    ///Bit 9 - Port output data
234    #[inline(always)]
235    pub fn odr9(&mut self) -> ODR_W<ODRrs> {
236        ODR_W::new(self, 9)
237    }
238    ///Bit 10 - Port output data
239    #[inline(always)]
240    pub fn odr10(&mut self) -> ODR_W<ODRrs> {
241        ODR_W::new(self, 10)
242    }
243    ///Bit 11 - Port output data
244    #[inline(always)]
245    pub fn odr11(&mut self) -> ODR_W<ODRrs> {
246        ODR_W::new(self, 11)
247    }
248    ///Bit 12 - Port output data
249    #[inline(always)]
250    pub fn odr12(&mut self) -> ODR_W<ODRrs> {
251        ODR_W::new(self, 12)
252    }
253    ///Bit 13 - Port output data
254    #[inline(always)]
255    pub fn odr13(&mut self) -> ODR_W<ODRrs> {
256        ODR_W::new(self, 13)
257    }
258    ///Bit 14 - Port output data
259    #[inline(always)]
260    pub fn odr14(&mut self) -> ODR_W<ODRrs> {
261        ODR_W::new(self, 14)
262    }
263    ///Bit 15 - Port output data
264    #[inline(always)]
265    pub fn odr15(&mut self) -> ODR_W<ODRrs> {
266        ODR_W::new(self, 15)
267    }
268}
269/**Port output data register (GPIOn_ODR)
270
271You can [`read`](crate::Reg::read) this register and get [`odr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`odr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
272
273See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA:ODR)*/
274pub struct ODRrs;
275impl crate::RegisterSpec for ODRrs {
276    type Ux = u32;
277}
278///`read()` method returns [`odr::R`](R) reader structure
279impl crate::Readable for ODRrs {}
280///`write(|w| ..)` method takes [`odr::W`](W) writer structure
281impl crate::Writable for ODRrs {
282    type Safety = crate::Unsafe;
283}
284///`reset()` method sets ODR to value 0
285impl crate::Resettable for ODRrs {}
stm32f1_staging/stm32f102/gpioa/odr.rs

stm32f1_staging/stm32f102/gpioa/
odr.rs
